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Method and circuit for sensing output from memory cell

A technology of storage unit and reference storage unit, which is applied in circuits, information storage, static memory, etc., can solve problems such as errors in sensing results, and achieve the effect of increasing sensing margins and reducing process fluctuations

Active Publication Date: 2009-09-09
TAIWAN SEMICON MFG CO LTD
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  • Claims
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Problems solved by technology

If the output current deviates slightly higher from its average state, the sensing result will be erroneous

Method used

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  • Method and circuit for sensing output from memory cell
  • Method and circuit for sensing output from memory cell
  • Method and circuit for sensing output from memory cell

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Embodiment Construction

[0034] image 3 A sensing circuit 300 according to an embodiment of the invention is shown. A sense amplifier 302 and two differential amplifiers (differential amplifier) ​​304, 306 are coupled to a memory array 308 and a reference array 310, wherein the memory array 308 includes a plurality of MRAM cells, and the reference array 310 includes a plurality of reference arrays. MRAM cells. The row of MRAM cells in memory array 308 is specified by word lines WL1 . . . WLn. The reference array 310 corresponding to the column of each word line WL contains at least one reference MRAM cell programmed as "1" and at least one reference MRAM cell programmed as "0". The column of MRAM cells in memory array 308 is specified by bit lines BL1 . . . BLn. A particular row of MRAM cells of memory array 308 may be selected by select signals on Y select lines YSEL1 . . . YSELN, which control select elements such as NMOS elements 312 and 314 .

[0035] When the MRAM cell 316 programmed to "1" ...

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Abstract

The present invention provides a method and circuit for sensing the output of a memory cell, wherein the memory cell is switchable between a high resistance state and a low resistance state. first applying a predetermined voltage to the memory cell to generate an output current reflecting a resistance state of the memory cell, and applying the predetermined voltage to at least two reference memory cells to generate a first reference current reflecting the high resistance state; A second reference current reflecting the low resistance state. Then provide a first phase difference value representing the gap between the output current and the first reference current, and a second phase difference value representing the gap between the output current and the second reference current. The first phase difference value is then compared with the second phase difference value to generate a digital output representing the resistance state of the memory cell. The invention can increase the sensing margin when reading the MRAM, and can self-compensate the load effect of the bit line by reducing the fluctuation of the manufacturing process.

Description

technical field [0001] The present invention relates to the design of integrated circuits, and more particularly to methods and systems for improving the sensing margin for reading data from memory cells. Background technique [0002] Magneto-resistive random access memory (MRAM) using magnetic elements has become one of the most popular technologies for storing data bits. Unlike general memory modules such as dynamic random access memory (DRAM) and static random access memory (SRAM) which use charges to store data bits, MRAM uses magnetic charges to store data bits. Unlike DRAM and SRAM, MRAM is a non-volatile device that does not require a fixed voltage source to retain stored information. Therefore, MRAM has particular advantages in portable products with limited power supplies, such as palmtop computers. [0003] MRAM cells are programmed to a high or low resistance state to store a data bit. Reading an MRAM cell traditionally uses only a sense amplifier to compare th...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G11C11/15G11C7/00H01L27/10
CPCG11C11/16G11C13/004G11C7/062G11C13/0004
Inventor 廖忠志
Owner TAIWAN SEMICON MFG CO LTD
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