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Method for producing semi-conductor device with capacitor

A semiconductor and device technology, applied in the final metal contact field of dynamic random access memory, can solve the problems of increased contact resistance of metal interconnection lines and plate electrodes, etc.

Active Publication Date: 2009-09-09
CONVERSANT IP N B 868
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Therefore, the contact resistance between the final metal interconnection line and the plate electrode may increase

Method used

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  • Method for producing semi-conductor device with capacitor
  • Method for producing semi-conductor device with capacitor
  • Method for producing semi-conductor device with capacitor

Examples

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Embodiment Construction

[0019] Hereinafter, detailed descriptions of specific embodiments of the present invention will be provided with reference to the accompanying drawings. Here, the thicknesses of layers and regions may be exaggerated in the drawings in order to clearly show said layers and regions. Also, when it is described that a layer is formed on a layer or a substrate, the layer may be directly formed on another layer or substrate or a third layer may be interposed therebetween. In addition, the same or similar reference numerals denote the same or similar elements even in different drawings.

[0020] Figure 3-7 is a cross-sectional view illustrating a method of manufacturing a semiconductor device including a capacitor according to an embodiment of the present invention. here, Figure 3-7 A cross-sectional view along the vertically extending direction of the bit lines is shown.

[0021] Such as image 3 As shown, a plurality of gate structures 17 for access transistors are formed on...

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PUM

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Abstract

A method of manufacturing a semiconductor device, comprising: providing a substrate structure, the substrate structure includes bit lines and capacitors formed to be separated from each other to varying degrees; forming first, second and third insulating layers on the bit lines, the second the insulating layer being a first etch stop layer; forming a second etch stop layer on the capacitor top electrode; forming a fourth insulating layer on the third insulating layer and the second etch stop layer; and performing a plurality of etching steps to expose the bit line surface and the upper surface of the capacitor.

Description

technical field [0001] The present invention relates to methods of fabricating semiconductor devices, and more particularly to methods of fabricating final metal contacts of dynamic random access memories (DRAMs) with cylindrical capacitors. Background technique [0002] Since dynamic random access memory (DRAM) has high capacitance and can freely input and output data, DRAM devices are widely used. Each DRAM device includes an access transistor and an accumulation capacitor. The data signal from the external circuit is accepted from the top electrode of the capacitor and the bit line through the final metal contact. [0003] figure 1 is a scanning electron microscope (SEM) micrograph illustrating a cross-sectional view of a typical DRAM device including final metal contacts. [0004] A first interlayer insulating layer ILD1 covering the bit line (BL) is formed on the substrate on which the bit line forming process is completed. Thereafter, a nitride-based etch stop laye...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/8242H01L21/768H01L21/311
CPCH01L27/10888H01L27/10852H01L21/76816H01L28/91H01L27/10885H10B12/033H10B12/482H10B12/485H10B99/00
Inventor ζŽη›Έι“η½—ε–„ι›„ζŽδΈœηƒˆε΄”δΈœζ±‚
Owner CONVERSANT IP N B 868