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Method for modeling MOS tube resistor

A technology of MOS tube and modeling method, which is applied in the fields of electrical digital data processing, special data processing applications, instruments, etc., can solve the problems of differences, inaccurate simulation analysis of MOS tubes, etc., and achieve the effect of accurate model

Inactive Publication Date: 2009-11-18
SEMICON MFG INT (SHANGHAI) CORP +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

But in fact, the resistance on the MOS tube includes contact resistance and parasitic resistance, and in the existing model expression, the parameter Rdc describing the drain resistance of the MOS tube and the parameter Rsc describing the source resistance of the MOS tube are both constants, but due to the contact The resistance will change with the number and position of the contact holes of the MOS tube, so the resistance of the MOS tube simulated by the existing model will be quite different from the real situation, resulting in inaccurate simulation analysis of the MOS tube

Method used

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  • Method for modeling MOS tube resistor

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Embodiment Construction

[0019] The invention measures the I-V characteristics of MOS tubes produced according to different layout structures, obtains resistance values ​​in various distribution situations, and obtains the variation of the resistance on the MOS tubes with the number of polysilicon roots and the width of a single polysilicon channel by fitting the resistance values changing relationship.

[0020] Such as figure 1 As shown, the present invention takes the modeling method of NMOS tube resistance as an example:

[0021] Step 1: Select MOS transistors with different channel widths as the MOS transistors to be modeled. For example, selecting NMOS transistors with a channel length of 0.13 microns and different channel widths, the channel width W ranges from 1 micron to 500 microns.

[0022] Step 2, for each MOS transistor, use at least one combination of polysilicon number and single polysilicon channel width for layout. As mentioned above, the layout structure of multiple polysilicon is ...

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Abstract

The invention discloses a method for modeling an MOS transistor resistance, which comprises the following steps: MOS transistors with different channel widths are selected and taken as MOS transistors to be modeled; aiming at every MOS transistor, the combined mode of the number of at least one polysilicon and the width of a single polysilicon channel is used for carrying out layout; the I-V characteristics of every MOS transistor generated according to the layout structure are measured; corresponding resistance is obtained according to the I-V characteristics; the obtained resistance is fitted and the relation of the resistance changing with the number of the polysilicon and the width of the polysilicon channel is obtained. The model obtained by the modeling method of the invention is closer to the measured value compared with that of the prior art, thus being more accurate.

Description

technical field [0001] The invention relates to a modeling method of MOS tube resistance. Background technique [0002] At present, for a MOS transistor with a larger size, such as a radio frequency MOS transistor, a layout structure of multiple polysilicon is often used in the layout design thereof. The layout structure of multiple polysilicon is to divide the MOS transistor with a certain channel width into multiple MOS transistors with the channel width as its divisor for equivalent replacement. The channel width of the MOS transistor after equalization is called The width of a single polysilicon channel, and the number of equal parts is equal to the number of polysilicon roots. For example, a MOS transistor with a channel width of 8um and a channel length of 0.13um can be equally divided into four single polysilicon MOS transistors with a channel width of 2um and a channel length of 0.13um, and the number of polysilicon is 4, and this 4 MOS tubes are connected in paral...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F17/50
Inventor 邵芳黄威森
Owner SEMICON MFG INT (SHANGHAI) CORP
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