Implementation method of high-speed digital filter and its structure

A technology of digital filter, implementation method, applied in the direction of digital technology network, impedance network, electrical components, etc.

Inactive Publication Date: 2007-11-28
BEIHANG UNIV
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  • Abstract
  • Description
  • Claims
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This is often at great expense to achieve what is required

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  • Implementation method of high-speed digital filter and its structure
  • Implementation method of high-speed digital filter and its structure
  • Implementation method of high-speed digital filter and its structure

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Embodiment Construction

[0032] The present invention will be further described in detail below in conjunction with the accompanying drawings.

[0033] The impulse response of the high-speed digital filter to be realized is h(n), where n=0, 1, 2...M-1, and M is the number of items of the impulse response h(n) of the digital filter.

[0034] The embodiment shown in FIG. 1 is aimed at the case where the input data is a digital signal. After the input digital signal x(k) is processed by the data splitting unit 11, it is divided into two digital signals x whose clock frequency is half of the clock frequency of the digital signal x(k) e (k) and x o (k). the x e (k) is a digital signal composed of even terms of said x(k). the x o (k) is a digital signal composed of odd terms of said x(k). x e (k) and x o (k) can be expressed by x(k) as:

[0035] x e (k)=x(2k), k=0, 1, 2...

[0036] x o (k)=x(2k+1), k=0, 1, 2...

[0037] the x e (k) is sent to the sub-filter A12 and the sub-filter C14, the impu...

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Abstract

The invention discloses a high-speed digital filter, which comprises the following parts: data detaching unit, which detaches high-speed digital signal x (k) into xe(k) and xo(k); four subfilters with subfilter A, subfilter B, subfilter C and subfilter D; delay unit, which proceeds unit delay for output signal of subfilter B; adder A, which adds output signal of delay unit and output signal of subfilter A; adder B, which adds the output signal of subfilter C and subfilter D; data parallel unit, which combines the output signal of adder A and adder B to produce the output signal of high-speed filter, wherein the collision response of subfilter A and subfilter D is he (n) and the collision response of subfilter B and subfilter C is ho (n); the output signal of subfilter A and subfilter C is xe (k) and the input signal of subfilter B and subfilter D is xo (k).

Description

technical field [0001] The invention relates to a digital filter, in particular to a method for realizing a high-speed digital filter in digital processing of broadband analog signals. Background technique [0002] At present, more and more applications involve the use of digital processing methods for analog signals. Filtering is a commonly used technique in signal processing. In the process of digital processing, the filtering of the signal is done by digital filter. In general, the operating frequency of the digital filter is consistent with the sampling frequency for sampling the analog signal. According to the sampling theorem, the sampling frequency must be greater than twice the bandwidth of the analog signal to ensure the authenticity of the signal. When the analog signal is a broadband signal, a very high sampling frequency is required, and the digital filter is also required to work at a very high clock frequency. This often requires paying a high price to achi...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03H17/02
Inventor 田进军刘林洪韬彭刚薛明华王振荣
Owner BEIHANG UNIV
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