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Method for raising fine quality of semiconductor chip

A yield, semiconductor technology, used in semiconductor/solid-state device manufacturing, photoengraving process of patterned surface, optics, etc., can solve the problems of yield reduction, negative photoresist residue, etc., and achieve the effect of improving yield

Inactive Publication Date: 2007-12-19
SEMICON MFG INT (SHANGHAI) CORP +1
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Problems solved by technology

[0008] Due to the use of double exposure in the wafer identification code area, the exposure energy is enhanced, which exposes the edges of several chips in the non-wafer identification code area connected to the wafer identification code area, forming negative photoresist residues, which makes the original soldering The area of ​​the bump disappears, resulting in a decrease in yield

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  • Method for raising fine quality of semiconductor chip
  • Method for raising fine quality of semiconductor chip
  • Method for raising fine quality of semiconductor chip

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Embodiment Construction

[0030] Due to the use of double exposure in the wafer identification code area, the exposure energy is enhanced, which exposes the edges of several chips in the non-wafer identification code area connected to the wafer identification code area, forming negative photoresist residues, which makes the original soldering The area of ​​the bump disappears, resulting in a decrease in yield. In order to improve the above situation, the present invention adopts the following method to perform double exposure on the wafer identification code area.

[0031] Please refer to shown in Fig. 3, the method for improving the yield rate of semiconductor chips of the present invention includes the following steps: coating a layer of negative photoresist S101 on the wafer surface; aligning the wafer identification code area with the photomask S102; Based on the exposure energy of the non-wafer identification code area, perform the first exposure S103 in the wafer identification code area; offset ...

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Abstract

A method for raising yield of semiconductor chip includes coating a negative light-blocking layer on surface of chip, aligning identification code region of chip to light cover, using exposure energy less than that of chip non-identification code region to carry out the first exposure on chip identification code region, making a shift from position of the first exposure and carrying out the second exposure on chip identification code region under the same condition, holding exposed part on adjacent connection edge of chip identification and non-identification code regions, developing unexposed part and preparing complete weld convex point.

Description

technical field [0001] The invention relates to the manufacture of semiconductor chips, in particular to a method for improving the yield rate of semiconductor chips. Background technique [0002] With the miniaturization of the semiconductor manufacturing process, the degree of integration of semiconductor components is getting higher and higher, and there are more and more circuit I / O lines, so more dense conductive connection points - solder bumps are required. The higher the density of solder bumps, the more difficult the processing technology, and the quality of solder bumps directly affects the yield of chips. [0003] Soldering bumps are made on the wafer. In order to clearly identify the wafer identification code during the formation of the soldering bumps, a double exposure method is used in the wafer identification code area to avoid the formation of soldering bumps. Refer to Figure 1A for details. -1E. [0004] Referring to FIG. 1A, in this process, a layer of n...

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G03F7/00H01L21/00
Inventor 王津洲李德君靳永刚
Owner SEMICON MFG INT (SHANGHAI) CORP