Phase alignment device, apparatus employing same and the method
A Phase Alignment, Phase Technology
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Embodiment 1
[0084]In this embodiment, the clock delay unit 3, the phase detection unit 1 and the pulse counting unit 2 are used to form a negative feedback loop to ensure that the phase difference between the output clock and the input clock is within an acceptable range. Through the connection and operation of the above-mentioned phase detection unit 1, pulse counting unit 2 and clock delay unit 3, the present invention can realize the output and output clock of the circuit 4 that will generate clock delay within several clock cycles. Phase alignment, at the same time, because when the clock input signal 5 or the clock output signal 6 disappears, the phase detection unit 1 does not generate the internal clock signal clk, that is, no longer controls the pulse counting unit to count, therefore, the pulse at this time The delay control signal output by the counting unit 2, that is, the value of the output clock delay control bus remains unchanged, so that the delay value of the clock delay u...
Embodiment 2
[0100] In another embodiment of the present invention, the circuit diagram of the phase detection unit 1 can also be as shown in Figure 4-1, the phase detection unit shown in Figure 4-1 is the same as the phase detection unit shown in Figure 4 The main difference is that a two-input NAND gate I277 is added to generate a phase-aligned signal to control the state of the internal clock signal clk output by the phase detection unit. At the same time, there are two counting control signals output by the phase detection unit shown in Figure 4-1, add_en and sub_en, and their values may be 1 or 0 respectively, and at most one of them can be 1 at the same time. To control the counting of the pulse counting unit connected to the phase detection unit, when the input and output clock signals are aligned, the values of the two counting control signals are both 0, and the pulse counting unit connected to the phase detection unit Counting is no longer performed. Correspondingly, the cir...
Embodiment 3
[0105] In yet another embodiment of the present invention, the circuit diagram of the phase detection unit 1 may also be as shown in FIG. 4-2 . Correspondingly, the circuit diagram of the pulse counting unit 2 may also be as shown in FIG. 5-2 . Among them, compared with the phase detection unit shown in Figure 4-1, the phase detection unit shown in Figure 4-2 is mainly different in that its output signal is only the internal clock signal clk, and there is no counting control signal add_en and sub_en, That is, the phase detection unit in this embodiment controls the counting of the pulse counting unit only by means of the outputted internal clock signal clk. At the same time, the difference between the pulse counting unit shown in Figure 5-2 and the pulse counting unit shown in Figure 5 and Figure 5-1 is mainly that, first, its input signal is only the internal clock signal clk, while Without counting control signals add_en and sub_en, as long as the internal clock signal is an...
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