Method of forming metal line in semiconductor device

Abstract

The invention discloses a method of forming a metal line in a semiconductor device comprising of forming an interlayer insulating film over a substrate, forming a via hole by selectively patterning the interlayer insulating film, forming a metal film over a surface of the interlayer insulating film including an inner portion of the via hole, filling the inner portion of the via hole with copper, deplating a copper layer exposed over the surface of the interlayer insulating film using reverse current to form a copper metal line and a recess region over the copper metal line, forming an upper insulating film over the surface of the interlayer insulating film including the recess region by deposition and forming an insulating cap layer selectively over only the recess region on the copper metal line by etching the upper insulating film. Therefore, an insulating layer is selectively formed on the metal line, especially a copper metal line, which is capable of reducing effective k of interlayer insulating film of whole Cu metal line, thereby reducing the RC delay of Cu metal line.

Description

[0001] This application claims the benefit of Korean Patent Application No. 10-2006-0086661 filed September 8, 2006, the entirety of which is hereby incorporated by reference as if set forth in its entirety. technical field [0002] The present invention relates to a method of forming a metal line in a semiconductor device, and more particularly to a method of forming a metal line in a semiconductor device capable of reducing the effective dielectric value k of an interlayer insulating film in the entire Cu metal line, by Selectively forming an insulating film on the metal lines reduces a delay of time constant (RC) of the metal lines. Background technique [0003] The miniaturization of metal lines and multilayer wiring has been accelerated along with the trend of high integration of semiconductor devices and reduction of chip size. In a logic device with a multilayer wiring structure, wiring delay is an important factor for device signal delay. Device signal delay is prop...

AI Technical Summary

Problems solved by technology

With the trend to miniaturize Cu metal lines, there is a disadvantage of increasing RC delay of back-of-line (BEOL) wiring due to the relatively high effective dielectric value (k) of the diffusion barrier film

In particular, when a metal having a high melting point such as Ta or W is used for an ultra-high miniaturized wiring layer including a via hole having a diameter of 0.1 μm and a metal line having a width of 0.1 μm, there is a risk of considerably increasing wiring resistance and contact resistance. shortcoming

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