Hardware 3DES for using digital power consumption compensation to prevent from power consumption power attack

Abstract

This invention relates to a hardware 3DES preventing power loss attack by digital power loss compensation used in intelligent card chips of a safety applied field, which utilizes a method for digital circuit power loss compensation to design two symmetrical 3DEG hardware circuits, one for getting ciphering result and the other for compensaing power loss to a first 3DEG circuit only playing the role of a coprocessor of ciphered operation in an intellident card, which can prevent power loss attack in the intelligent card field at the same time when realizing 3DEG ciphered operation at high speed.

Description

technical field [0001] The present invention is mainly applied to smart cards in high-security application fields, such as telecommunication cards, financial cards, and social security cards, and can also be applied to various security chips that need to perform high-speed 3DES calculations and need to prevent power consumption attacks on 3DES. Background technique [0002] The National Bureau of Standards (NIST) announced an encryption algorithm developed by IBM in 1977, and approved it as a data encryption standard used by non-confidential departments, referred to as DES (Data Encryption Standard). Since its publication, it has been beyond national borders and has become the most commonly used encryption algorithm for commercial confidential communication and computer communication in the world. The key of DES is 56 bits, and the key is too short. 3DES is a variant of DES, which adopts triple encryption and extends the key of DES to 128 bits, which has higher security. ...

AI Technical Summary

Problems solved by technology

Power consumption attacks make many encryption algorithms that are proved to be very safe mathematically have great hidden dangers in hardware implementation

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