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Configurable cache system depending on instruction type

A cache and instruction-type technology, applied in memory systems, memory architecture access/allocation, instruments, etc.

Inactive Publication Date: 2008-05-14
TEXAS INSTR INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

This problem is especially tricky for L1 caches due to their relatively small size

Method used

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  • Configurable cache system depending on instruction type
  • Configurable cache system depending on instruction type

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Embodiment Construction

[0016] [0012] The following description is directed to various embodiments of the invention. While one or more of these embodiments may be preferred, the disclosed embodiments should not be construed, or otherwise used, to limit the scope of the disclosure, including the claims. In addition, those skilled in the art should understand that the following description has broad application, and the description of any embodiment is only an illustrative description of this embodiment, and is not meant to limit the scope of the disclosure including the claims to this embodiment.

[0017] [0013] FIG. 1 shows a preferred embodiment of a system 50 including a processor 51 coupled to system memory 68. The processor preferably includes fetch logic 52 , decode logic 54 , load / store unit 56 , processor instruction execution logic unit 58 , coprocessor 60 and cache subsystem 62 . Cache subsystem 62 includes a first level cache ("L1") coupled to a second level cache ("L2"). According to at ...

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Abstract

A processor comprises decode logic that determines an instruction type for each instruction fetched, a first level cache, a second level cache coupled to the first level cache, and control logic operatively coupled to the first and second level caches. The control logic preferably causes cache linefills to be performed to the first level cache upon cache misses for a first type of instruction, but precludes linefills from being performed to the first level cache for a second type of instruction.

Description

technical field [0001] [0001] The present invention relates to a microprocessor cache device and method useful in a data communication system. Background technique [0002] [0002] On-chip caches are used in various microprocessor designs to improve performance by storing frequently used information in fast on-chip cache memory. Performance is improved because information can be fetched quickly during program execution. Some systems have multiple levels of cache. "L1" caches are typically relatively small in size, but very fast in access time. "L2" caches are typically larger in capacity than L1 caches, but have slower access times than L1 caches. [0003] [0003] When encountering a "load" instruction that attempts to fetch data from a target memory location, the processor first determines whether the target data is already resident in the L1 cache. If the data exists in the L1 cache (called a cache "hit"), the target data is fetched from the L1 cache. If the data is not...

Claims

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Application Information

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IPC IPC(8): G06F12/00
CPCG06F2212/1021G06F12/0897G06F9/30043G06F9/3824G06F12/0888G06F12/0811G06F9/3885
Inventor T·M·特朗R·A·小咖瑞贝M·S·希那扣达P·K·米勒
Owner TEXAS INSTR INC