P type MOS transistor and method for forming same

Abstract

The invention discloses a method of adjusting the threshold voltage of a P-shaped MOS transistor which comprises the following steps of: forming a P-shaped MOS transistor on a semiconductor substrate and a second N-shaped ion implantation in the S / D region of the P-shaped MOS transistor. The invention also provides a P-shaped MOS transistor and a method for forming the same, wherein the method comprises the following steps: providing a semiconductor substrate which comprise a I region and a II region concentric with the I region, wherein, the II region covers 15 percent to 20 percent of the area of the whole semiconductor substrate; forming a P-shaped MOS transistor on the semiconductor substrate, and a second N-shaped ion implantation into the source and drain extension region of the II region on the semiconductor substrate. The implantation of the N-shaped ion into the II region of the semiconductor substrate of the invention increases the doping concentration thereby inhibiting the reduction of the threshold voltage of the P-shaped MOS transistor in the II region of the semiconductor substrate.

Description

technical field [0001] The invention relates to the field of semiconductor devices, in particular to a P-type MOS transistor and a forming method thereof. Background technique [0002] At present, due to the increasing integration of integrated circuits, the size of devices is getting smaller and smaller, and the feature size of devices is developed from 0.13um to below 0.10um. The feature size of the device refers to the gate length of the MOS transistor. Therefore, the gate length of the MOS transistor has a decisive influence on the performance of the device. In the prior art, the gate of the MOS transistor is formed by plasma etching on the semiconductor substrate. Oxide layer, polysilicon layer, silicide and silicon nitride layer are formed, but due to uneven etching, the gate length of MOS transistors in different regions on the semiconductor substrate will be uneven, especially in the edge region of the semiconductor substrate, which The gate length of the MOS transi...

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Problems solved by technology

[0006] The problem solved by the present invention is that the plasma etches unevenly on the semiconductor substrate, especially the edge region of the semiconductor substrate, i.e. the second region, which causes the gate length of the MOS transistor to be formed by etching to decrease, thereby resulting in the formation of the edge region of the semiconductor substrate. The threshold voltage of MOS transistors is lower than that of the central region of the semiconductor substrate, resulting in lower yields

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