Line swapping scheme to reduce back invalidations, device and system

Abstract

The invention relates to a line swapping scheme to reduce back invalidations in a snoop filter. In an embodiment, a method is provided. The method of this embodiment provides steps as follows: receiving a request for data from a processor of a plurality of processors, determining a cache entry location based, at least in part, on the request, storing the data in a cache corresponding to the processor at the cache entry location, and storing a coherency record corresponding to the data in an affinity corresponding to the cache.

Description

technical field [0001] Embodiments of the present invention relate to reducing later invalid row swapping schemes in snoop filters. Background technique [0002] As a method of increasing the computing power of new computer systems, the use of multiple processors, or processors with multiple cores, is increasingly common. Multiprocessor and multicore systems share system resources such as system memory and storage. Multiple processors or cores typically access the same data in memory or storage and attempt to utilize this data concurrently. To achieve this aspect, multiprocessor and multicore systems track data usage to maintain data coherency. One aspect of maintaining data coherency in a multiprocessor system is ensuring that the data cached in each processor is consistent. For example, each processor may alter data in its cache before writing the data back to system memory. If another processor requests changed data from system memory before this data is written back...

AI Technical Summary

Problems solved by technology

These large snoop filters take up a lot of space and add complexity and thus cost to the hub controller

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