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Information processing apparatus, information processing method and computer program

A technology of information processing equipment and processors, applied in the direction of multi-programming devices, etc., can solve the problem of reducing processing performance and achieve the effect of no time lag

Inactive Publication Date: 2008-09-10
SONY CORP +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Interrupt handling that tends to cause cache corruption or memory access location corruption necessarily takes more processing time from the PPU and thus degrades processing performance

Method used

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  • Information processing apparatus, information processing method and computer program
  • Information processing apparatus, information processing method and computer program
  • Information processing apparatus, information processing method and computer program

Examples

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Embodiment 1

[0057] First, referring to FIG. 8 , an example of a structure employable in an information processing device in an embodiment of the present invention will be described. An information processing device according to the present invention operating in an asymmetric multiprocessor environment similar to the foregoing description includes a single PPU (Authoritative Processor Unit) and eight SPUs (Cooperative Processor Units).

[0058] As shown in FIG. 8 , the PPU 211 is built in a PPE (Authoritative Processor Element) 210 , while each of the eight SPUs 221 is built in a separate SPE (Syndicated Processor Element) 220 . The PPU 211 functions as a master processor to control the OS, and the eight SPUs 221 are slave processors each engaging in execution of a specific type of processing assigned thereto.

[0059] The PPE 210 includes a two-level cache memory composed of an L1 cache memory 212 and an L2 cache memory 213 . The SPEs 220 each include a storage space called a local stor...

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PUM

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Abstract

The invention provides an information processing apparatus, an information processing method and a computer program. A sub-processor different from the main processor executing control in the operating system (OS) is designated to control a device driver corresponding to a communication unit and thus, the communication control is executed by the sub-processor in response to an interrupt originating from a network card functioning as the communication unit in an information processing apparatus equipped with a plurality of processors and engaged in communication via a network. The structure enables the main processor to execute data processing with a high level of efficiency without a time lag in the data processing.

Description

[0001] Cross References to Related Applications [0002] The present invention contains subject matter related to Japanese Patent Application JP2007-002986 filed in the Japan Patent Office on Jan. 11, 2007, the entire content of which is hereby incorporated by reference. technical field [0003] The present invention relates to an information processing device, an information processing method, and a computer program. More specifically, the present invention relates to an information processing device adopting a multiprocessor configuration that performs data processing using a plurality of processors, an information processing method employed in such an information processing device, and a computer program that prevent For example, the reduction in data processing efficiency of communication processing. Background technique [0004] Today, in applications that perform various types of data processing by causing a plurality of processors to operate simultaneously, informati...

Claims

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Application Information

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IPC IPC(8): G06F9/46
Inventor 久曾神宏河村佑二
Owner SONY CORP