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Dot clock generating circuit, semiconductor device, and dot clock generating method

A technology for generating circuits and clock generators, used in instruments, static indicators, cathode ray tube indicators, etc., to solve problems such as inability to ensure point clock switching, high point clock switching, unstable clock frequency time periods, etc.

Inactive Publication Date: 2008-11-26
RENESAS ELECTRONICS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] However, even after solving the problem of periods of unstable clock frequency, it is not guaranteed that a dot clock switch occurs at the start of a frame
Further, for frames that cannot display normal images, there is a high possibility that dot clock switching occurs while a frame is being displayed

Method used

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  • Dot clock generating circuit, semiconductor device, and dot clock generating method
  • Dot clock generating circuit, semiconductor device, and dot clock generating method
  • Dot clock generating circuit, semiconductor device, and dot clock generating method

Examples

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Embodiment 1

[0019] figure 1 It is a block diagram showing an example structure of a dot clock generating circuit according to Embodiment 1 of the present invention. figure 1 The dot clock generation circuit (dot clock generation device) 1 shown in FIG. 1 includes a programmable clock generator (clock generator) 10 and a clock division ratio holding unit (frequency division ratio holding unit) 20.

[0020] The programmable clock generator 10 outputs a dot clock generated by dividing the frequency of the reference clock through the output terminal 12. Further, the programmable clock generator 10 can switch its frequency division ratio according to the frequency division ratio (frequency division ratio information) of the clock input via the input terminal 13. Furthermore, when its frequency division ratio is switched, the programmable clock generator 10 does not generate an unstable clock period. There are various techniques to prevent the generation of an unstable clock period, such as the te...

Embodiment 2

[0050] In Embodiment 2, an implementation in which the function of adjusting the timing for changing the clock frequency is added to the dot clock generation circuit of Embodiment 1 will be described.

[0051] 4 is a block diagram showing an example structure of a dot clock generating circuit according to Embodiment 2 of the present invention. The dot clock generation circuit 8 of FIG. 4 is configured with the dot clock generation circuit 1 of Embodiment 1, and has a clock division ratio switching timing adjustment unit (adjustment unit) 30 added thereto.

[0052] The clock division ratio switching timing adjustment unit 30 includes an offset register 31, a comparison / determination unit 32, and a counter 33.

[0053] The offset register 31 holds an offset (time), and the timing of changing the clock frequency is delayed by the offset.

[0054] The comparison / determination unit 32 compares the offset with the count value of the counter 33, and if they are equal, outputs the write v...

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Abstract

This invention refers to dot clock generating circuit, semiconductor device, and dot clock generating method. A dot clock generating circuit includes a division ratio holding unit to hold division ratio information specifying a clock division ratio and to output the division ratio information synchronously with switching of frames and a clock generator to divide the frequency of a reference clock according to the division ratio information output from the division ratio holding unit, thereby generating a dot clock.

Description

Technical field [0001] The present invention relates to a circuit for generating a dot clock, which is a reference clock used when a display device displays dots. Background technique [0002] Recently, there has been a display device that switches and displays a plurality of images with different resolutions. Such a display device switches its resolution according to an instruction from a user or via communication between devices. At this time, the display device needs to switch the dot clock used to control the display timing. [0003] Various dot clock switching methods have been implemented and suggested. One method is to use a clock generation circuit that has a PLL (Phase Locked Loop) inserted therein to switch the PLL frequency division ratio. Using this method, after changing the frequency division ratio, it does not immediately switch to the ideal clock frequency, but a time period of tens to hundreds of milliseconds, during which the clock frequency is unstable. During ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G09G5/18
CPCG09G5/18G09G5/36G09G2360/02G09G3/20G09G5/12G09G5/32
Inventor 加藤隆
Owner RENESAS ELECTRONICS CORP