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Chip stack package structure

A packaging structure and chip stacking technology, applied in the direction of electrical components, electric solid devices, circuits, etc., can solve the problems of miniaturization and high density of packaging structure, thick chip stacking thickness, high process cost, etc. Low efficiency, solve the effect of low packaging density

Inactive Publication Date: 2008-12-03
CHIPMOS TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0008] The purpose of the present invention is to provide a chip stack packaging structure to solve the problems of the above-mentioned known technologies, such as the thickness of the chip stack is too thick, the process cost is too high, and the miniaturization and high density of the packaging structure are limited.

Method used

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Embodiment Construction

[0095] In order to make the above and other objects, features, advantages and embodiments of the present invention more comprehensible, several chip stack packaging structures are provided as preferred embodiments for further description.

[0096] Please refer to FIG. 1 , which is a schematic cross-sectional view of a chip stack package structure 100 according to a first preferred embodiment of the present invention.

[0097] The chip stack package structure 100 includes: a substrate 101 , a first chip 102 , a patterned circuit layer 105 , a second chip 106 , a conductive component 120 , a sealing resin 122 and a plurality of external connection terminals 111 .

[0098] The substrate 101 has a first surface 118 and a second surface 119 opposite to the first surface 118 . In a preferred embodiment of the present invention, the substrate 101 is constituted by a lead frame, a printed circuit board or a die carrier. In this embodiment, the base material 101 is a printed circuit b...

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PUM

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Abstract

The invention discloses a chip stack packaging structure, comprising: a substrate, a first chip, a second chip, a patterned circuit layer and a conductive component, wherein, the substrate is provided with a first surface and an opposite second surface, and the first chip is positioned at the first surface of the substrate and electrically connected with the substrate. The second chip is positioned on the first chip and provided with a second driving surface, wherein, the second driving surface is equipped with at least one second welding pad. The patterned circuit layer is positioned on the second driving surface of the second chip, matched with the second welding pad and electrically connected with the substrate by the conductive component.

Description

technical field [0001] The invention relates to a semiconductor package structure, in particular to a stack package structure. Background technique [0002] With the sharp increase in the demand for functions and applications of electronic products, packaging technology is also developing in the direction of high-density miniaturization, single-chip packaging to multi-chip packaging, and two-dimensional to three-dimensional scaling. Among them, System In Package is a better way to integrate chips with different circuit functions. It uses Surface Mount Technology (SMT) technology to integrate different chip stacks on the same substrate, so as to effectively reduce the packaging cost. area. It has the advantages of small size, high frequency, high speed, short production cycle and low cost. [0003] Please refer to FIG. 5 , which is a cross-sectional view of a known chip stack package structure 500 . The chip stack package structure 500 includes a substrate 510 , a first ch...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L25/00H01L25/065H01L23/488
CPCH01L2924/15311H01L2224/32145H01L25/0657H01L2224/16145H01L2224/4824H01L2224/73207H01L2224/73265H01L2224/48227H01L2224/73215H01L2224/32225H01L24/73H01L2224/0401H01L2224/06135H01L2224/06136H01L2924/181
Inventor 沈更新林峻莹
Owner CHIPMOS TECH INC
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