Efficient execution of memory barrier bus commands

Abstract

The disclosure is directed to a weakly-ordered processing system and method of executing memory barriers in weakly-ordered processing system. The processing system includes memory and a master device configured to issue memory access requests, including memory barriers, to the memory. The processing system also includes a slave device configured to provide the master device access to the memory, the slave device being further configured to produce a signal indicating that an ordering constraint imposed by a memory barrier issued by the master device will be enforced, the signal being producedbefore the execution of all memory access requests issued by the master device to the memory before the memory barrier.

Description

[0001] Related Application Cross-References [0002] This patent application claims priority to Provisional Application No. 60 / 781,091, filed March 10, 2006, entitled "Efficient Execution of Memory Barrier Bus Commands," and states The provisional application is assigned to its assignee and is expressly incorporated herein by reference. technical field [0003] The present invention relates generally to processing systems, and more particularly, to techniques for efficiently processing memory barrier bus commands in a processing system. Background technique [0004] Computers and other modern processing systems have revolutionized the electronics industry by enabling complex tasks to be performed with just a few keystrokes. These complex tasks often involve several devices that communicate with each other using a bus in a fast and efficient manner. The bus provides a shared communication link between devices in the processing system. [0005] Depending on the particular ...

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Problems solved by technology

Therefore, the next memory operation after the memory barrier is delayed until every memory device accessible by the processor completes all outstanding memory operations

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