Method and apparatus for decoding low density parity check code

A low-density parity and decoding device technology, applied in error detection coding, coding, code conversion, etc. using multi-bit parity bits, can solve the problem of no decoder, etc., to reduce the number of iterations and decoding. The effect of complexity

Inactive Publication Date: 2009-07-01
SAMSUNG ELECTRONICS CO LTD +1
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  • Abstract
  • Description
  • Claims
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Problems solved by technology

[0046] Although the CN_C BP algorithm can provide faster convergence speed and consume less storage units, it has not received as much attention as the traditional BP algorithm (see Comparative Document 2, J.Dielissen, A.Hekstra, and V.Berg .Low cost LDPC decoder for DVB-S2.2006.Philips Research, High Tech Campus 5, 5656 AEEindhoven, The Netherlands.)
In particular, there is currently no decoder based on variable node message vectors and the CN_CBP algorithm

Method used

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  • Method and apparatus for decoding low density parity check code
  • Method and apparatus for decoding low density parity check code
  • Method and apparatus for decoding low density parity check code

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Embodiment Construction

[0079] First, the basic composition of the decoder according to the present invention will be described.

[0080] The overall structure of the LDPC decoder

[0081] The overall structure of the LDPC code decoder according to the present invention is as follows image 3 shown. The decoder may include: a variable node message memory 301 , a memory access controller 302 , a node calculation unit 303 and a decoding termination controller 304 . The input of the decoder is the channel information vector, and the output is the hard-decision codeword bits. exist image 3 In , thick arrows represent data flow, and thin arrows represent control signals. The function description of each unit in the decoder is as follows:

[0082] Variable node message memory 301: stores variable node message vectors; under the control of the memory access controller, the node computing unit can perform read and write operations on the component.

[0083] Memory access controller 302: control the re...

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Abstract

The invention discloses a decoding device of low density parity check code (LDPC), which comprises a variable node message storage; a controller used for controlling the read and write operation of a node calculation unit to the variable node message storage and controlling the iteration process of a LDPC decoder; and a node calculation unit used for updating the messages of check nodes and variable nodes and judging the messages. The node calculation unit comprises a variable message generation unit used for calculating the variable message required by a check message calculation unit; a check message calculation unit used for updating the check message; a variable node message update unit used for updating the corresponding variable node message; a hard decision calculation unit used for calculating the hard decision message corresponding to the variable node; a parity check unit used for calculating the check bit and outputting a result to a decoding termination controller. The decoding device can meet the performance requirement and simultaneously reduce the decoding complexity of check code and reduce the iteration times.

Description

technical field [0001] The present invention relates to the coding and decoding technology of the digital communication system, in particular to a decoding method of a low-density parity check code and a device using the method. Background technique [0002] For communication systems, channel coding technology is a key technology to ensure reliable communication in noisy channels. Some current communication standards have adopted modern codes such as Turbo codes and low-density parity-check codes (LDPC for short) as their predecessor error correction codes. In the IEEE 802.16e Mobile Global Interoperability Microwave Access Standard, Turbo codes and LDPC codes are used as optional preceding error correction codes at the same time. In addition, the second-generation digital satellite television broadcasting system (Digital video broadcasting satellite version 2, abbreviated as DVB-S2), the terrestrial digital television broadcasting system (Digitaltelevision terrestrial broa...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03M13/11
CPCH03M13/1134H03M13/6505H03M13/1165H03M13/1114H03M13/6544H03M13/1131H03M13/1137H03M13/114H03M13/00H03M13/11
Inventor 王单汝聪翀魏立军朴范镇朴盛镇
Owner SAMSUNG ELECTRONICS CO LTD
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