Address interpretation method, apparatus and single-board
An address decoding and address technology, applied in the field of communication, can solve the problem of limited address space and achieve the effect of expanding the address space
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Embodiment 1
[0029] figure 1 A schematic flow chart of an address decoding method provided in this embodiment, as shown in figure 1 shown, including:
[0030] S101. Receive a high-order address value sent by a central processing unit to access an address to be accessed, and convert the high-order address value into a high-order address signal for accessing an address to be accessed.
[0031] When the address to be accessed accessed by the central processor is not within the address space that the central processor can directly access, the central processor cannot directly send a complete address signal for accessing the address to be accessed through its own address line. Therefore, the central processing unit can split the complete address signal for accessing the address to be accessed into two parts, one part is the high address signal, and the other is the low address signal; the high address signal is the signal of the high address line for accessing the address to be accessed, and t...
Embodiment 2
[0040] figure 2 A schematic structural diagram of a single board provided for this embodiment, including a CPU, a memory, and a decoding device connected to the CPU and the memory. The decoding device can be implemented by a programmable logic device or a field programmable gate array. In this embodiment, an EPLD (Erasable Programmable Logic Device, Erasable Programmable Logic Device) as an example for description.
[0041] Such as figure 2 As shown, the EPLD is connected with the address line, data line, chip select signal and other control lines of the memory; on the other hand, the EPLD is connected with the address line, data line, chip select signal and other control lines of the CPU. Wherein, the central processing unit includes 23 address lines (Addr[22:0]), 16-bit bit width (Date[15:0]), and the address space that the CPU can directly select or access through its own address lines is 8MB. The address space of the memory is 32MB, and the memory includes 25 address ...
Embodiment 3
[0056] This embodiment provides an address decoding device, which is connected to a central processing unit and hardware devices through a bus, and can communicate with the central processing unit and hardware devices through a bus.
[0057] Such as Figure 5 As shown, the address decoding device includes:
[0058] The high-order address module 51 is used for receiving the high-order address value sent by the central processing unit, and converting the high-order address value into a level signal.
[0059] Its specific implementation, for example, can use register 511, receive and preserve the high order address value that central processing unit sends from bus line, this high order address value is the value of the high order address line of the address that central processing unit will visit; Then use conversion unit 513 Convert the upper address value received and saved by the register 511 into a level signal.
[0060] The low-order address module 53 is used to receive th...
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