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Method and chip for serial communication

A serial communication and chip technology, applied in the field of electronic communication, can solve problems such as waste of bus resources, and achieve the effects of low cost, high efficiency and good industrial value

Inactive Publication Date: 2008-07-16
许新朋
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

This way of vacating one bit causes a waste of bus resources

Method used

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  • Method and chip for serial communication
  • Method and chip for serial communication
  • Method and chip for serial communication

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0037] As shown in Figure 1, the method for serial communication in the present invention includes the following steps: 1. system initialization, after opening the serial port, first set the serial port chip communication parameters and FIFO interrupt trigger level; 2. send communication data frames, distinguish address data and application The flag bit of the data, and cache all the data into the cache of the operating system driver and the FIFO cache on the chip. The steps include: setting the parity bit to "1", then sending the address, and then setting the parity Bit is set to "0", send data; ③ Receive communication data frame.

[0038] According to the configuration requirements of common non-real-time multitasking operating systems such as Windows and Linux, especially affected by wiring costs and distances, 9600 and 19200 are the two most commonly used baud rates in industrial applications. Taking the baud rate of 9600 as an example, various configurations in the presen...

Embodiment 2

[0054] As shown in Figure 1, the method for serial communication in the present invention includes the following steps: 1. system initialization, after opening the serial port, first set the serial port chip communication parameters and FIFO interrupt trigger level; 2. send communication data frames, distinguish address data and application The flag bit of the data, and cache all the data into the cache of the operating system driver and the FIFO cache on the chip. The steps include: setting the parity bit to "1", then sending the address, and then setting the parity Bit is set to "0", send data; ③ Receive communication data frame.

[0055] Taking the baud rate of 19200 as an example, various configurations in this embodiment are described. Moreover, the 9600 baud rate can also be set with such parameters.

[0056] The settings of the serial port driver are as follows:

[0057] Read Interval Timeout Read Interval Timeout=5ms;

[0058] Read timeout constant Read Total Timeou...

Embodiment 3

[0067] As shown in Figure 2, the method for serial communication in the present invention includes the following steps: 1. system initialization, after opening the serial port, first set the serial port chip communication parameters and FIFO interrupt trigger level; also need to query and configure the timer accuracy Timer Resolution. ② Send the communication data frame, distinguish the flag bit of the address data and the application data, and cache the flag bit and all data of the difference address data and the application data to the buffer memory of the operating system driver and In the FIFO buffer on the serial communication chip, the steps include: setting the parity bit to "1", then sending the address, then setting the parity bit to "0", and sending the data; after sending the address and data, both Waiting is required, and the waiting time is set according to the length of the character to be sent and the baud rate. ③ Receive communication data frame.

[0068] For...

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PUM

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Abstract

The invention discloses a method for serial communication which comprises the following steps that: the system is initialized, a communication data frame is sent and then is received; when the system is initialized, serial port chip communication parameters and an FIFO interruption trigger level are firstly set after the serial port is opened; when the communication data frame is sent, mark bits of the address data and the application data are distinguished, the steps comprise that: an even-odd parity bit is set as '1', then the address is sent; then the even-odd parity bit is set as '0', and the data is sent; under the condition of the support of the serial port communication chip, the distinguished mark bits of the address data and the application data as well as the entire data are buffered into a cache of an operation system driving program and an FIFO cache on the serial port communication chip. The invention solves the time problem encountered when the mark bits are switched, synchronously ensures that the speed reporting to the upper layer application after the industrial control machine receives the data is improved by four to sixteen times than the default speed, and enlarges the address space at the same time.

Description

technical field [0001] The invention belongs to the field of electronic communication, in particular relates to a high-efficiency serial data communication method and provides a chip used in the method. Background technique [0002] Due to its simple design and low cost, the RS485 protocol is still widely used in the field of industrial data communication. High-speed devices such as upper-level industrial computers and low-speed devices such as lower-level single-chip computers constitute a distributed system. Due to the limitations of the RS-485 bus and cost, upper-level industrial computers The master-slave communication with the lower microcontroller is adopted, especially in order to save wiring costs, half-duplex communication is mostly used in industry, usually using 11-bit mode, followed by start bit, 8-bit data bit, parity bit, stop bit bit, the serial port of the lower-level single-chip microcomputer works in mode 3, and each single-chip microcomputer terminal has a...

Claims

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Application Information

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IPC IPC(8): G06F13/42
Inventor 许新朋李改霞
Owner 许新朋