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Low speed DMA interface chip system and internal memory access method

A memory access, SoC technology, applied in the SoC field to facilitate integration and reuse

Inactive Publication Date: 2012-09-05
WUXI ZGMICRO ELECTRONICS CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Since the DMA controller reads the data of the low-speed module through the APB bus, which involves clock domain conversion, bus arbitration, etc., the waiting time for each data is relatively long, so the speed sometimes cannot meet the instantaneous speed of the low-speed module. requirements, resulting in the slow module requiring a considerable cache

Method used

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  • Low speed DMA interface chip system and internal memory access method
  • Low speed DMA interface chip system and internal memory access method
  • Low speed DMA interface chip system and internal memory access method

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Experimental program
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Embodiment Construction

[0017] Signal width input Output Owned clock xxx_dma_wreq 1 enter xxx_clk xxx_dma_wstop 1 enter xxx_clk xxx_dma_wdata data width enter xxx_clk dma_xxx_wready 1 output xxx_clk

[0018] Among them, xxx_dma_wreq is the write request signal sent by the low-speed module to the DMA controller. xxx_dma_wstop is the write stop signal sent by the low-speed module to the DMA controller. xxx_dma_wdata is the data to be written into the memory sent by the low-speed module to the DMA controller. dma_xxx_wready is the write ready signal sent by the DMA controller to the low-speed module.

[0019] Figure 4 It is a logical schematic diagram of an interface of a low-speed module writing memory according to an embodiment of the present invention. like Figure 4 As shown, the write memory interface logic includes a first D flip-flop working under the low-speed clock xxx_clk, a synchronizer and a second D flip-flop working under th...

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Abstract

The invention provides a system on a chip (SoC) and a corresponding DMA memory access method thereof. The system comprises a low-speed module, a DMA controller, a bus arbitration unit and a memory and is characterized in that a DMA interface is adopted between the low-speed module and the DMA controller; and the DMA interface adopts an inversion signal as a handshake signal so as to lead the low-speed module to send a DMA request to the memory through the bus arbitration unit. The invention adopts the inversion signal as the handshake signal to conveniently support the DMA request crossing the clock domain, etc. In addition, the DMA module standardizes the request into the internal data bus signal for facilitating integration and multiplexing. As an APB bus is not adopted, the waiting time of data read-write can be predicted.

Description

technical field [0001] The present invention relates to a system on a chip, in particular to the memory access of a low-speed module. Background technique [0002] With the development of the system on chip (SOC), more and more modules are integrated in a chip, and its demand for memory access is also getting higher and higher. Therefore, how to provide a simple and unified memory access mechanism for each module is becoming more and more important for the efficiency, reliability and reusability of chip design. Generally speaking, most high-speed modules access memory using a bus similar to AHB (Advanced High-performance Bus), while low-speed modules mostly access memory through a dedicated DMA (direct memory access) controller. figure 1 A prior art solution for accessing memory by a low-speed module is illustrated. like figure 1 As shown, the controller uses a bus like the APB (Advanced Peripheral Bus) to read its registers from the low-speed module, and then access t...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F13/28
Inventor 李晓强
Owner WUXI ZGMICRO ELECTRONICS CO LTD