Semiconductor device and forming method thereof

Abstract

The invention relates to a semiconductor device and a forming method thereof. The semiconductor device comprises a substrate on which an active region is defined, a shallow trench isolator positioned on the substrate and directly surrounding the active region, a grid electrode, a source electrode and a drain electrode which are positioned on the active region, and a hard mask positioned above the juncture of the shallow trench isolator and the active region.

Description

technical field [0001] The present invention relates to a semiconductor device and its forming method, in particular to a semiconductor device with protected shallow trench isolation and its forming method. Background technique [0002] In order to increase the carrier mobility of the gate channel in the semiconductor device, the current technology generally uses the method of adjusting the strain force of the gate channel to increase or decrease the strain force of the gate channel, and finally to improve the carrying capacity of the gate channel. Flow rate. For example, in a PMOS device, a set of trenches can be formed in the source / drain regions on both sides of the gate channel, and then filled with SiGe material etc. to replace part of the silicon substrate. Therefore, the strained silicon (strained-Si) is created by using the effect that the Ge atom is larger than the Si atom, so as to generate an additional compressive force in the gate channel, so as to promote the ...

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Problems solved by technology

Additionally, if image 3 As shown, the shallow trench isolation 130 will be damaged again when the capping layer 103 is removed

The resulting gap 132 plus the damage 131 not only makes the purpose of using the SiGe layer 111 to increase the compressive force of the gate channel severely offset by the space defined by the gap 131, but also self-aligns the metal silicide (self- aligned silicide, salicide) steps, the metal silicide may also extend along the direction of the gap 131 into the silicon substrate 110, causing other adverse effects that are difficult to control

[0005] In addition, since the shallow trench isolation 130 adjacent to the active region 120 is not covered by the capping layer 103, its top surface will also be lost in the aforementioned etching or cleaning steps, so that the subsequent removal of the covering layer After the capping layer 103 on the source region 120, the top surface of each STI 130 is unequal to the substrate surface, that is, the top surface of the STI 130 adjacent to the active region 120 will be lower than the top surface of the STI 130 adjacent to the active region 120. The top surface of the shallow trench isolation 130 of the source region 121 increases the difficulty of subsequent processes

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