Clock synchronization method and system
A clock synchronization and clock technology, applied in time division multiplexing systems, transmission systems, electrical components, etc., can solve the problems of increased clock synchronization deviation, master-slave clocks cannot meet the synchronization accuracy requirements between master-slave clocks, etc., to achieve The effect of reducing synchronization deviation
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no. 1 example
[0090] Figure 4 The block diagram of the first embodiment of the first acquisition unit provided by the embodiment of the present invention, the first acquisition unit includes:
[0091] The acquisition subunit 401 is configured to acquire the synchronization deviation between the master and slave clocks sent by the slave clock.
[0092] In the embodiment of the present invention, after the master clock realizes clock synchronization, there are two methods for obtaining the synchronization deviation between the master and slave clocks sent by the slave clock, specifically:
[0093] 1. The master clock sends a request message to the slave clock, and the request message includes requesting the slave clock to send a synchronization deviation message between the master and slave clocks.
[0094] After receiving the request message, the slave clock sends the synchronization deviation between the master and slave clocks to the master clock;
[0095] The master clock receives the ...
no. 2 example
[0099] Figure 5 The block diagram of the second embodiment of the first acquisition unit provided by the embodiment of the present invention includes:
[0100] The acquisition subunit 501 is configured to receive the synchronization deviation between the master and slave clocks sent by the slave clock.
[0101] The acquisition subunit 501 has the same function as the acquisition subunit 401, and details are not repeated here.
[0102]The average value calculation subunit 502 is configured to calculate the average value of the synchronization deviation between the master and slave clocks, and use the average value of the synchronization deviation between the master and slave devices as a reference value of the synchronization deviation between the master and slave clocks.
no. 3 example
[0103] Image 6 The block diagram of the third embodiment of the first acquisition unit provided by the embodiment of the present invention includes:
[0104] The acquisition subunit 601 is configured to receive the synchronization deviation between the master and slave clocks sent by the slave clock.
[0105] The acquisition subunit 601 has the same function as the acquisition subunit 401, and details are not repeated here.
[0106] The weight coefficient obtaining subunit 602 is configured to obtain the weight coefficient of the slave clock.
[0107] The synchronization deviation reference value calculation subunit 603 is configured to calculate the synchronization deviation reference value between the master and slave clocks according to the weight coefficient of the slave clock.
[0108] Figure 7 The embodiment block diagram of the weight coefficient acquisition subunit provided for the embodiment of the present invention, the weight coefficient acquisition subunit inc...
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