Logic self-loading method and system for field programmable gate array of embedded system

Abstract

The invention discloses a logic self-loading method and a system for a field programmable gate array of an embedded system. The method comprises the following steps of binding a single-board logic guiding module with a single-board logic downloading module to obtain an automatic loaded logic starting module; starting a field programmable gate array by the automatic loaded logic starting module; and loading logic files of the field programmable gate array by the automatic loaded logic starting module according to a recorded loading mode. The system comprises a binding module and the automatic loaded logic starting module, wherein the binding module is used for binding the single-board logic guiding module with the single-board downloading module to obtain the automatic loaded logic starting module; and the automatic loaded logic starting module is used for starting the field programmable gate array and loading the logic files of the field programmable gate array in the recorded loading mode. Therefore, through the binding mode, application program codes are not needed to be compiled and constructed again when relative factors such as content, downloading mode and the like of single logic are changed.

Description

technical field [0001] The present invention relates to a Field Programmable Gate Array (Field Programmable GateArray, FPGA for short) of an embedded system, in particular to a method and system for self-loading FPGA logic of an embedded system. Background technique [0002] In the single-board software development process, FPGA has become an indispensable core device on the single-board hardware. At present, there are many types of FPGAs, and there are many loading methods. Such as: serial loading, parallel loading, JATG (Joint Test Action Group, the Chinese name is joint test behavior organization) loading, JATG is an international standard test protocol (IEEE 1149.1 compatible), which can test the hardware of chips with JTAG interface The circuit performs boundary scan and fault detection. The previous method of loading FPGA on the board software is to put the FPGA loading method in the application storage space, and bind it to the board software through the hybrid comp...

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Problems solved by technology

[0005] The technical problem to be solved by the present invention is to provide a method and system for self-loading of FPGA logic in an embedded system, so as to solve the problem in the prior art that the FPGA logic can only be upgraded by first upgrading the application program and not by upgrading the FPGA logic alone

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