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Branch checkout for reduction of non-control flow commands

A control instruction and non-control technology, applied in the direction of program control design, concurrent instruction execution, address formation of the next instruction, etc., can solve problems such as speed drop and delay

Inactive Publication Date: 2010-06-30
STMICROELECTRONICS BEIJING R& D
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

As a result, delays may occur while the target instruction is being fetched and processed by the initial stages of the pipeline, resulting in an overall decrease in speed as instructions are processed through the pipeline

Method used

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  • Branch checkout for reduction of non-control flow commands
  • Branch checkout for reduction of non-control flow commands
  • Branch checkout for reduction of non-control flow commands

Examples

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Embodiment Construction

[0018] As mentioned above, branch instructions slow down the microprocessor pipeline. Some microprocessors include hardware component(s) such as branch history table (branch history table, BHT) and / or branch target buffer (branch target buffer, BTB). ), which provides branch prediction information that can be used to increase the speed of the pipeline. Some microprocessors, such as superscalar microprocessors, use branch history tables and branch target buffers to improve performance. A superscalar microprocessor is a processor that utilizes several functional units within the microprocessor core, such as the arithmetic logic unit and / or other functional units, to execute more than one instruction in one cycle. In a superscalar microprocessor, several instructions may be fetched in parallel from the instruction cache. While an instruction fetch is being performed, the BHT and / or BTB's branch prediction information for the fetched instruction may be checked concurrently. For ...

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Abstract

The invention relates to branch checkout for reduction of non-control flow commands. Some micro processors are used for checking branch forecast information in a branch history list and / or a branch target buffer. To check the branch forecast information, the micro processors can identify which commands are control flow commands and which are non-control flow commands. To reduce power consumption in the branch history list and / or the branch target buffer, the branch history list and / or the branch target buffer can be used for checking the branch forecast information corresponding to control flow commands, but not the branch forecast information corresponding to non-control flow commands.

Description

technical field [0001] The present invention relates generally to microprocessors, and in particular to reducing power consumption for branch prediction. Background technique [0002] A microprocessor is an electronic device that performs various computing operations in response to instructions implementing a computer program. A common technique for implementing a computer program is to send a plurality of instructions in a predetermined sequence to the execution unit of a microprocessor, and then execute the instructions sequentially. In some cases, the program jumps out of sequence to execute an instruction that is not the next instruction in the sequence. One example of an instruction that can cause execution to jump out of the sequence is a branch instruction. When executing a branch instruction, the microprocessor can jump to the target instruction identified by the branch instruction, and the next step for the microprocessor to execute is the target instruction inste...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F9/38
CPCG06F9/3806G06F9/32G06F9/3844
Inventor 王凯峰孙红霞吴永强
Owner STMICROELECTRONICS BEIJING R& D
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