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Multi-core processor

A processor and multi-core technology, applied in a variety of digital computer combinations, etc., can solve the problems of limited expansion capability and limited chip power consumption, and achieve the effect of easy expansion

Inactive Publication Date: 2011-11-09
HUNAN UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The method of improving digital signal processing capability by increasing the main frequency is limited by chip power consumption, heat dissipation and manufacturing process, and the expansion capability is limited

Method used

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Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0034] figure 1 Include a plurality of processor sets 1, and described processor set comprises a master processor 2 and several slave processors 3, master processor and slave processor and slave processor and slave processor are connected by local bus 4, The processor sets and between the processor sets and the debugging configuration unit are connected by the global bus 5 and the switching unit (SWITCH) 6, and some peripherals or hardware acceleration units may be integrated on the multi-core processor. figure 1 Not shown in , these peripherals or hardware acceleration units can also be connected to the debug configuration unit and the processor set through the global bus 5 .

[0035] The master processor 2 controls the instructions and data carried out from the processor 3, and the slave processor may not have a program memory and an instruction fetch unit, and the master processor sends the super long instruction word to the slave processor 3 through the instruction bus in ...

Embodiment 2

[0056] figure 1 The central global bus 5 can not only transmit multipoint-to-multipoint data communication between processor sets, but also transmit control information such as configuration, debugging, and tracking between the debugging configuration unit and the processor set. The multi-core processor system can work in two modes: debug mode and non-debug mode. Regardless of the debug mode or the non-debug mode, before the multi-core processor starts to run the code, the debug configuration unit 9 is responsible for configuring the program memory of the main processor in all processor sets on the entire multi-core processor, that is, the The code executed in is loaded into the program memory of the host processor. At the same time, debugging the configuration unit may also need to initialize the register files, data memory or other special registers of the master processor and the slave processor in the processor set.

[0057] After a power-on reset, the multi-core process...

Embodiment 3

[0071] according to figure 2 The bus configuration shown in includes global bus 5, global bus switching unit 6 and local bus 4. All slave processors 3-A, ..., 3-D in a processor set 1-A jointly complete SIMD or MIMD tasks under the control and coordination of the master processor 2-A , and different sets of processors can handle different tasks. In order to increase the processing capability of the multi-core processor, or to increase the number of slave processors in each processor set, the number of processor sets may also be increased. The increase in the number of slave processors in the processor set does not change the structure of the bus and the bus input and output ports of the master processor and the slave processor. Increasing the number of processor sets does not change the structure of the global bus and the global bus switching unit, so the processor capability of the multi-core processor of the present invention is easy to expand.

[0072] If you want to fi...

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PUM

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Abstract

The invention provides a multi-core processor which comprises a plurality of processor sets and a debugging configuration unit, wherein the processor sets are in row distribution, each processor set comprises a main processor and a plurality of slave processors, and all the main processor and the slave processors are ultra-long instruction word processors; the number of the processor sets is M*N,and the M*N processor sets form M*N arrays of the processor sets; M*N exchange units are in one-to-one correspondence to the M*N processor sets; an exchange unit is arranged at each node of the M*N arrays; upper and lower or left and right adjacent exchange units as well as the processor sets and the corresponding exchange units are all connected through global buses; and the first row of exchange units in the M*N exchange units are all connected with the debugging configuration unit through the global buses. The invention can realize that a plurality of processors in each processor set can seamlessly cooperate.

Description

technical field [0001] The invention belongs to the field of computer and digital communication, and relates to a multi-core processor. All main processors and slave processors in the multi-core processor are ultra-long instruction word processors. technical background [0002] The rapid development of digital communication, especially wireless communication, puts forward higher and higher requirements for the ability of digital signal processing. The method of increasing the digital signal processing capability by increasing the main frequency is limited by chip power consumption, heat dissipation and manufacturing process, and the expansion capability is limited. Very long instruction word (VLIW) and multi-core processor structure can well expand the ability of digital signal processor. [0003] We know that a parallel computer or an ultra-long computer uses a network to connect some general-purpose processors or computers to provide powerful processor capabilities. The a...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F15/17
Inventor 陈容吴桂清王卫平
Owner HUNAN UNIV
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