Linear feedback shift register (LFSR)-based random test device for external storage interface

A technology for random testing and external storage, used in static memory, instruments, etc.

Active Publication Date: 2010-11-24
TSINGHUA UNIV
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  • Abstract
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In the patent application with the application number 200910083767.4 and the name. Random test program generation method and system and design verificati...

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  • Linear feedback shift register (LFSR)-based random test device for external storage interface
  • Linear feedback shift register (LFSR)-based random test device for external storage interface
  • Linear feedback shift register (LFSR)-based random test device for external storage interface

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Embodiment Construction

[0022] Embodiments of the present invention are described in detail below, examples of which are shown in the drawings, wherein the same or similar reference numerals designate the same or similar elements or elements having the same or similar functions throughout. The embodiments described below by referring to the figures are exemplary only for explaining the present invention and should not be construed as limiting the present invention.

[0023] The present invention mainly lies in that, based on the pseudo-random numbers generated by the LFSR, the generated pseudo-random numbers are converted into random test excitations conforming to the AHB bus protocol, and random test excitations for external storage interfaces are generated, thereby realizing random testing for external storage interfaces.

[0024] Specifically, the AHB bus signals include: clock signal HCLK, global reset signal HRESET, slave device selection signal HSEL, read and write signal HWRITE, transmission le...

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Abstract

The invention provides a linear feedback shift register (LFSR)-based random test device for an external storage interface. The device comprises a pseudo random number generating module for generating a pseudo random number, a pseudo random number register module for storing the pseudo random number, a test actuation producing and outputting module for generating a random test actuating signal according to the pseudo random number and a test module for comparing a read data signal with data written in the same address of an external storage and counting total failure times. The LFSR-based random test device for the external storage interface of the invention takes the LFSR as a pseudo random number generator and converts the produced pseudo random number into random test actuation, which is accordant with an advanced high-performance bus (AHB) protocol, of the external storage interface so that the random test of the external storage interface is realized.

Description

technical field [0001] The invention relates to the field of random test circuit design, in particular to a random test device based on an LFSR external storage interface. Background technique [0002] In recent years, due to the greatly increased computational complexity of computers, the difficulty of circuit verification has been greatly increased, and the verification complexity and workload also account for a large proportion of the entire design workload. Currently in SoC (System on Chip, system on chip) development, verification has gradually become a bottleneck in SoC development. Memory system plays an important role in SoC design. The slow growth of memory performance relative to processor performance makes the problem of memory system design more and more critical. The verification of memory interface has become a very important step in SoC system design. [0003] The external memory interface is based on the AHB (Advanced High performance Bus, advanced high-perf...

Claims

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Application Information

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IPC IPC(8): G11C29/56
Inventor 李兆麟陈佳佳叶剑飞魏炽频郑庆伟李圣龙王芳
Owner TSINGHUA UNIV
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