Semiconductor device manufacturing method

Abstract

Disclosed is a semiconductor device production method, which comprises the steps of: forming a pillar-shaped first-conductive-type semiconductor layer on a planar semiconductor layer; forming a second-conductive-type semiconductor layer in a portion of the planar semiconductor layer underneath the pillar-shaped first-conductive-type semiconductor layer; forming a gate dielectric film and a gate electrode having a laminated structure of a metal film and an amorphous silicon or polysilicon film, around the pillar-shaped first-conductive-type semiconductor layer; forming a sidewall-shaped dielectric film on an upper region of a sidewall of the pillar-shaped first-conductive-type semiconductor layer and in contact with a top of the gate electrode; forming first and second sidewall-shaped dielectric films on a sidewall of the gate electrode; forming a second-conductive-type semiconductor layer in an upper portion of the pillar-shaped first-conductive-type semiconductor layer; forming a metal-semiconductor compound on the second-conductive-type semiconductor layer formed in the portion of the planar semiconductor layer underneath the pillar-shaped first-conductive-type semiconductor layer; forming a metal-semiconductor compound on the second-conductive-type semiconductor layer formed in the upper portion of the pillar-shaped first-conductive-type semiconductor layer; forming a metal-semiconductor compound on the gate electrode; forming a contact on the second-conductive-type semiconductor layer formed in the portion of the planar semiconductor layer underneath the pillar-shaped first-conductive-type semiconductor layer; and forming a contact on the second-conductive-type semiconductor layer formed in the upper portion of the pillar-shaped first-conductive-type semiconductor layer.

Description

technical field [0001] The invention relates to a semiconductor device and a manufacturing method thereof. Background technique [0002] Semiconductor integrated circuits, especially integrated circuits using MOS transistors, have entered into high integration. With high integration, MOS transistors used therein have been miniaturized to the nanometer range. However, as the miniaturization of MOS transistors progresses, it is difficult to suppress a leak current, and there is a problem that the occupied area of ​​a circuit cannot be reduced in order to secure a necessary amount of current. In order to solve the above-mentioned problems, a Surrounding Gate Transistor (SGT), which has a structure in which the source, gate, and drain are arranged in a direction perpendicular to the substrate, and the gate surrounds the columnar semiconductor layer, is known. Proposed (eg, Patent Document 1, Patent Document 2, Patent Document 3). [0003] Since the SGT arranges the channel re...

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Problems solved by technology

In addition, since a large on-current flows, low resistance is also required at the contact part

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