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Semiconductor device and manufacturing method thereof

A manufacturing method and semiconductor technology, applied in semiconductor/solid-state device manufacturing, semiconductor devices, transistors, etc., can solve problems such as difficulty in suppressing leakage current

Active Publication Date: 2012-02-15
UNISANTIS ELECTRONICS SINGAPORE PTE LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

As the miniaturization of MOS transistors progresses, the suppression of leakage current becomes more difficult, and there is a problem that it is difficult to reduce the occupied area of ​​the circuit in order to ensure the required amount of current.

Method used

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  • Semiconductor device and manufacturing method thereof
  • Semiconductor device and manufacturing method thereof
  • Semiconductor device and manufacturing method thereof

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Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0182] Fig. 35(a) is a plan view of the NMOS SGT formed by the present invention, and Fig. 35(b) is a cross-sectional view (b) of Fig. 35(a) along cutting line A-A'. Next, an NMOS SGT formed using the present invention will be described with reference to FIG. 35 .

[0183] On the BOX layer 120 formed on the Si substrate 111, a planar silicon layer 12 is formed, a columnar silicon layer 113 is formed on the planar silicon layer 12, and a gate insulating film 124 and a gate insulating film 124 are formed around the columnar silicon layer 113. electrode 141 . The planar silicon layer 112 under the columnar silicon layer 113 forms + source diffusion layer 200 . N + Drain diffusion layer 201. N + A contact portion 174 is formed on the source diffusion layer 200, N + The contact portion 173 is formed on the drain diffusion layer 201 , and the contact portion 172 is formed on the gate wiring 141 b extending from the gate electrode 141 a.

[0184] Figure 36 It is a cross-sect...

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Abstract

The present invention provides a method for manufacturing surrounding gate transistors to obtain low-resistance structures of the source, drain, and gate, as well as the desired gate length, source, drain shape, and diameter of the columnar semiconductor . The manufacturing method of the semiconductor device comprises: a step of forming a columnar first conductivity type semiconductor layer; a step of forming a second conductivity type semiconductor layer under the columnar first conductivity type semiconductor layer; A step of forming a gate insulating film and a gate electrode; a step of forming an insulating film on the upper part of the gate and on the sidewall of the upper part of the columnar first conductivity type semiconductor layer; a step of forming an insulating film on the sidewall of the gate; A step of forming a second conductivity type semiconductor layer on the upper portion of the first conductivity type semiconductor layer; and forming a metal-semiconductor compound on the second conductivity type semiconductor layer and the gate formed on the upper and lower portions of the columnar first conductivity type semiconductor layer step.

Description

technical field [0001] The invention relates to a semiconductor device and a manufacturing method thereof. Background technique [0002] Semiconductor integrated circuits, especially integrated circuits using MOS (Metal Oxide Semiconductor; Metal Oxide Semiconductor) transistors, tend to be more highly integrated. Along with this high integration, the miniaturization of MOS transistors used therein has progressed to the nanometer (nano) field. As the miniaturization of MOS transistors progresses, it becomes more difficult to suppress leakage current, and there is a problem that it is difficult to reduce the occupied area of ​​a circuit in order to secure a required amount of current. In order to solve this problem, there is a proposal for a Surrounding Gate Transistor (SGT) in which the substrate arranges the source, gate, and drain in a vertical direction, and the gate surrounds the columnar semiconductor layer. (eg Patent Documents 1, 2, 3). [0003] Patent Document 1: ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L29/786H01L21/28H01L21/336
CPCH01L29/66787H01L29/78642
Inventor 舛冈富士雄新井绅太郎中村广记工藤智彦
Owner UNISANTIS ELECTRONICS SINGAPORE PTE LTD