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Semiconductor packaging structure and manufacture process thereof

A technology of manufacturing process and packaging structure, applied in semiconductor/solid-state device manufacturing, semiconductor devices, semiconductor/solid-state device components, etc., can solve problems such as substrate packaging colloid surface pollution, protective glue residue, etc.

Active Publication Date: 2012-08-29
ADVANCED SEMICON ENG INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] The purpose of the present invention is to provide a semiconductor packaging structure and its manufacturing process, which can avoid the problem of surface contamination of the substrate, lower chip or packaging colloid caused by the residual protective glue in the existing manufacturing process after grinding

Method used

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  • Semiconductor packaging structure and manufacture process thereof
  • Semiconductor packaging structure and manufacture process thereof
  • Semiconductor packaging structure and manufacture process thereof

Examples

Experimental program
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Embodiment Construction

[0061] In the present invention, a grid wall with sufficient thickness is arranged on the package mother board, wherein the grid wall can be integrated in the existing substrate manufacturing process. For example, the solder cap layer on the bearing surface of the package mother board is thickened to form The grid wall, and the thickness of the grid wall is preferably controlled to be greater than the thickness of the thinned underlying chip. After the lower layer chip is bonded to the package mother board and filled with primer, a coating layer will be fully coated on the package mother board to facilitate subsequent grinding steps. Since the thickness of the grid wall is larger than the thickness of the thinned lower chip, when the lower chip is ground until one end of the through-silicon via is exposed, the cladding layer originally located above the grid wall and above the lower chip is already in the grinding process. Therefore, there will be no residual coating layer and...

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Abstract

The invention discloses a semiconductor packaging structure and a manufacture process thereof. The manufacture process of the semiconductor packaging structure comprises the steps of: configuring a packaging mother board on a support tool, wherein the packaging mother board is provided with a grid wall arranged vertically on the packaging mother board and the grid wall defines a plurality of concave parts on the packaging mother board; respectively jointing a plurality of first chips to the concave parts of the packing mother board, wherein each first chip is provided with silicon penetratingguide holes inside; forming first primer between each first chip and the corresponding packaging mother board; forming a cladding layer on the support tool; thinning the cladding layer and the grid wall from the upside of the support tool until the cladding layer above the grid wall and the first chip is completely removed; jointing a plurality of second chips to the first chips; forming second primer between each second chip and the corresponding first chip; separating the support tool from the packaging mother board, and cutting the packaging mother board to obtain a plurality of packaging units.

Description

technical field [0001] The present invention relates to a semiconductor packaging technology, and in particular, to a stacked semiconductor element packaging technology. Background technique [0002] In today's information society, the design of electronic products is moving towards the trend of being light, thin, short, and small, so packaging technologies such as stacked semiconductor device packaging that are conducive to miniaturization have been developed. [0003] Stacked semiconductor component packaging is to use vertical stacking to package multiple semiconductor components in the same package structure, which can increase the packaging density to miniaturize the package, and can use the three-dimensional stacking method to shorten the signal transmission between the semiconductor components. The path length can be increased to improve the speed of signal transmission between semiconductor elements, and semiconductor elements with different functions can be combined...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/50H01L21/58H01L23/13H01L23/29
CPCH01L2224/73204
Inventor 陈仁川张惠珊张文雄张唯农
Owner ADVANCED SEMICON ENG INC