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Semiconductor structure and method for forming dual-damascene structure

A dual damascene structure, semiconductor technology, applied in the direction of semiconductor devices, semiconductor/solid-state device manufacturing, semiconductor/solid-state device components, etc., can solve the problem of polluting photoresist, and achieve the effect of avoiding the slope effect

Inactive Publication Date: 2011-05-11
SEMICON MFG INT (SHANGHAI) CORP +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0012] The problem to be solved by the present invention is to provide a method for forming a dual damascene structure, which solves the problem of slope effect and nitrogen diffusion polluting the photoresist existing in the existing forming method

Method used

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  • Semiconductor structure and method for forming dual-damascene structure
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  • Semiconductor structure and method for forming dual-damascene structure

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Embodiment Construction

[0033] In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, the present invention can be implemented in many other ways different from those described here, and those skilled in the art can make similar extensions without violating the connotation of the present invention, so the present invention is not limited by the specific implementations disclosed below.

[0034] Secondly, the present invention is described in detail using schematic diagrams. When describing the embodiments of the present invention in detail, for the convenience of explanation, the cross-sectional view showing the device structure will not be partially enlarged according to the general scale, and the schematic diagram is only an example, and it should not be limited here. The protection scope of the present invention. In addition, the three-dimensional space dimensions of length, width and depth should be inc...

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Abstract

The invention provides a semiconductor structure and a method for forming a dual-damascene structure. The method comprises the following steps: providing a semiconductor substrate with a metal wiring layer; forming a first etch stop layer and a first inter-layer dielectric layer on the metal wiring layer; forming first photoresist patterns on the surface of the first inter-layer dielectric layer;forming a contact hole through etching; removing the first photoresist patterns; forming a second etch stop layer in the contact hole; forming a second inter-layer dielectric layer and a protective layer on the surface of the first inter-layer dielectric layer; forming second photoresist patterns on the surface of the protective layer; forming a trench through etching; removing the second photoresist patterns and the second etch stop layer in the contact hole; and etching the first etch stop layer at the bottom of the contact hole to expose the metal wiring layer. In the invention, as the twointer-layer dielectric layers are respectively used for manufacturing the contact hole and the trench, and the second etch stop layer is filled in the contact hole, the etching process stops on the second etch stop layer when the trench is formed, thus avoiding the slope effect.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a method for forming a double damascene structure and a semiconductor structure. Background technique [0002] With the rapid development of semiconductor device manufacturing technology, semiconductor devices already have deep submicron structures. As the number of devices contained in integrated circuits continues to increase, and the size of devices continues to shrink due to the increase in integration, the high-performance, high-density connections between devices are not only performed in a single interconnection layer, but also in multiple layers. interconnection between. Therefore, a multilayer interconnection structure is generally provided in which a plurality of interconnection layers are stacked on each other with an interlayer insulating film interposed therebetween for connecting semiconductor devices. In particular, a multi-layer interconnection structu...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/768H01L23/528
Inventor 王琪周鸣
Owner SEMICON MFG INT (SHANGHAI) CORP
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