Instructions for enabling processor wait states

Abstract

In one embodiment, the present invention includes a processor having a core with decode logic to decode an instruction prescribing an identification of a location to be monitored and a timer value, and a timer coupled to the decode logic to perform a count with respect to the timer value. The processor may further include a power management unit coupled to the core to determine a type of a low power state based at least in part on the timer value and cause the processor to enter the low power state responsive to the determination. Other embodiments are described and claimed.

Description

technical field [0001] The present invention relates to instructions for enabling processor wait states. Background technique [0002] As processor technology advances, processors become available to take advantage of greater numbers of cores. For efficient software execution, these cores can be tasked to execute different threads of a single application. Such an arrangement is called cooperatively threaded software. In modern cooperatively threaded software, one thread typically waits for another thread to finish. By convention, processors running waiting threads waste active power while waiting. Furthermore, the time to wait may be indeterminate, and thus the processor may not know how long it should wait. [0003] Another mechanism to enable the core to wait is to place the core in a wait state such as a low power state. To accomplish this task, an operating system (OS) is invoked. The OS can execute a pair of instructions called the MONITOR instruction and the MWAI...

AI Technical Summary

Problems solved by technology

However, there is significant overhead in entering the OS to execute these instructions

This overhead comes in the form of high wait times and can also add complexity as OS scheduling issues can cause waiting threads to not be the next scheduled thread when they exit the wait state

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