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Cache system for reducing data transmission

A caching system and data transmission technology, applied in the computer field, to achieve the effect of reducing data transmission

Active Publication Date: 2012-09-19
XI AN UNIIC SEMICON CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Achieving better performance seems to take considerable effort and cost, but most low-cost electronic systems will not allow it

Method used

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  • Cache system for reducing data transmission
  • Cache system for reducing data transmission
  • Cache system for reducing data transmission

Examples

Experimental program
Comparison scheme
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Embodiment Construction

[0027] The present invention will be described in further detail below in conjunction with the accompanying drawings.

[0028] see figure 1 and figure 2 As shown, it describes the basic principles of the invention. The transfer buffer chip MBu (Buffer) that reduces data transfer is placed between the microcontroller / microprocessor MC and the storage subsystem. The storage subsystem includes DRAM and Flash, etc. The previous approach required any communication between the microcontroller / microprocessor and the memory subsystem to pass all information to be processed from the memory subsystem to the microcontroller / microprocessor and vice versa. The transmission buffer chip MBu in the present invention cannot process these information automatically, thereby reducing the communication between the storage subsystem and the microcontroller / microprocessor.

[0029] The invention is especially suitable for storage subsystems, so in figure 1 And in the following illustrations, t...

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Abstract

The invention provides a cache system for reducing data transmission, which comprises a transmission cache, a subsystem and a microprocessor or a microcontroller, wherein the transmission cache is electrically connected with the microprocessor or the microcontroller, and the transmission cache is electrically connected with the subsystem. The invention provides the cache system for reducing the data transmission, wherein the microprocessor or the microcontroller A and the transmission cache B are interconnected through an AB bus, the transmission cache B is connected with the subsystem C through a BC bus, on average, the data volume from the A to the B (written) on the AB bus is smaller than the data volume from the B to the C (written) on the BC bus by about 10 percent in the normal working mode of the system; and on average, the data volume from the B to the A (read) on the AB bus is smaller than the data volume from the C to the B (read) on the BC bus by about 10 percent in the normal working mode of the system.

Description

【Technical field】 [0001] The invention relates to the field of computer technology, in particular to a cache system for reducing data transmission. 【Background technique】 [0002] Today's communication or computer systems contain an intelligent unit that controls all communication and data transfer within the system. Such a control unit may be a microprocessor or a microcontroller or both. If a data transfer is performed within such a system, it will result in a large amount of data being transferred through the microcontroller or microprocessor. Imagine loading the data in the cache into the microprocessor. Large amounts of data will be transferred from the memory system to the microprocessor through the microcontroller, or directly from the memory system to the microprocessor in some systems to update the cache information. [0003] For another example, when low-power products such as tablets or notebooks are in deep sleep mode, refreshable DRAM content will be stored in...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F13/16
Inventor 濮必得
Owner XI AN UNIIC SEMICON CO LTD