Iterative decoding of blocks with cyclic redundancy checks
A technology of cyclic redundancy check and iterative decoding, which is applied in the direction of error correction/error detection, code conversion, encoding, etc. by combining multiple code structures, can solve the level battery that is not effectively solved, the stop rule is complicated, and the complexity Increased power consumption and other issues, to achieve the effect of fast operation, small chip area and power consumption, and reduce complexity
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[0054] As described herein above, there can be "miss events" and "false alarm events" caused by early stopping rules with iterative decoding. It is best to keep the probability of "miss events" and "false alarm events" as low as feasible in designing early stopping rules. The "miss event" probability exists in all three types of stopping rules: hard and soft decision rules and CRC rules. However, the CRC rule has the unique advantage of exhibiting essentially zero "false alarm event" probability.
[0055] It should be noted that, given the CRC attachment to a block, there are numerous ways to design different stopping rules with different reliability levels. A naive approach may get a floor on the code block error probability, which is ultimately undesirable. This is further exacerbated when the transport block is divided into sub-blocks and the iterative decoding of the stop rule applied to each sub-block. A focus of certain described embodiments is to avoid such outcomes....
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