Semiconductor memory device

Abstract

The invention relates to a semiconductor memory device. According to one embodiment, a semiconductor memory device performs writing of data to a semiconductor memory element in response to a request to write the data with a specified logical block address from a host and performs writing of valid data to the semiconductor memory element for compaction according to a log-structured method. The semiconductor memory device adjusts a frequency of the writing response to a request from the host and a frequency of the writing for compaction according to a predetermined ratio.

Description

[0001] Cross References to Related Applications [0002] This application is based on and claims the benefit of priority from Japanese Patent Application No. 2010-031797 filed on February 16, 2010 and Japanese Patent Application No. 2010-206116 filed on September 14, 2010, the entire contents of which are hereby incorporated by reference. technical field [0003] Embodiments described herein relate generally to semiconductor memory devices. Background technique [0004] Due to the increase in capacity of a NAND type flash memory (referred to as NAND memory), which is one type of semiconductor memory chips, semiconductor memory devices using semiconductor memory chips are widely used in recent years. When writing to NAND memory, the NAND memory needs to be erased before writing. Erasing of the NAND memory is performed in blocks such as 512KB in units. This is significantly larger than 4KB, which is a data size more frequently used when writing in response to a request from ...

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Problems solved by technology

However, when compressed, the bandwidth of NAND memory is squeezed due to the reading and writing of valid data, which results in a significant slowdown in the response speed to data write requests from the host

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