Decoder, data driver and display device

Abstract

Disclosed is a decoder, receiving the first and the second reference voltage groups and selecting a reference voltage in accordance with a received digital signal, including a first sub-decoder receiving the first reference voltage group, a second sub-decoder receiving the second reference voltage group 20B, and a third sub-decoder receiving a reference voltage selected by the second sub-decoder and outputting the selected reference voltage to the first sub-decoder or an output terminal of the decoder. The first sub-decoder includes a transistor of a first conductivity type having a back gate supplied with a first power supply voltage, the second sub-decoder includes a transistor of the first conductivity type having a back gate supplied with a second power supply voltage, and the third sub-decoder includes a transistor of the first conductivity type having a back gate supplied with a first power supply voltage.

Description

technical field

[0001] The present invention relates to a decoder which inputs a plurality of voltage signals and selectively outputs according to digital signals, and a data driver of a display device using the decoder. Background technique

[0002] Figure 19 It is a diagram for explaining an example of a typical configuration of a decoding circuit of a data driver for a display element of a display panel by selecting one voltage (gradation voltage) from a plurality of reference voltages based on a video data signal. Also in Figure 19 For ease of description, the following structure is illustrated: the image data signal is a 3-bit digital signal (High indicates the high-order side power supply VDD, and Low indicates the low-order side power supply VSS), and the 3-bit data and its complementary signals D1, D1B, D2, D2B, D3, and D3B select and output one of the eight reference voltages V1-V8 in a competitive manner. That is, there are 14 pMOS transistors (transfer transist...

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