Step-type gan gate device and preparation method thereof

Abstract

The invention provides a stepped GaN gate device and its preparation method. The preparation method comprises the following steps: providing a substrate, growing a GaN channel layer and a barrier layer, defining gate, source, and drain regions; removing the source-drain region barrier layer, and grow a doped GaN layer in the source and drain regions, and the upper surface of the doped GaN layer is higher than the barrier layer; deposit an isolation layer, and define the isolation layer in the vertical direction as a side wall layer; except the side wall layer in the gate area The area is divided into a zero etching area and a zero step area, and the zero etching area, the step area and the gate area have the same extension direction; the isolation layer of the zero etching area is removed; and a gate metal layer is deposited in the gate area. The present invention forms the step-type field plate of the grid through the isolation sidewall process, and at the same time reduces the size of the grid, and also improves the withstand voltage performance of the device by using the step-type field plate. The size of the grid in the invention is controllable, and the precision of the photolithography equipment is not high; the stepped field plate structure and the grid structure are formed together, and the process conditions are simple and feasible, and the repeatability is high.

Description

technical field

[0001] The invention relates to the field of semiconductor integrated circuit manufacturing, in particular to a stepped GaN gate device and a preparation method. Background technique

[0002] GaN high electron mobility transistors (HEMTs) have good application prospects in high-voltage scenarios due to their large energy band gaps.

[0003] At present, in order to further improve the withstand voltage performance of GaN HEMT devices, generally by increasing the distance L from the gate to the drain gd , or add a field plate structure above the gate toward the drain to adjust the electric field distribution at the drain end and enhance the withstand voltage of the device.

[0004] However, increasing the gate-to-drain distance L gd The process method not only increases the device area, which is not conducive to the miniaturization of the device, but also increases the access resistance and weakens the frequency performance of the device; while the process me...

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