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Step-type gan gate device and preparation method thereof

A stepped, gated technology, applied in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., can solve the problem of inability to effectively improve the withstand voltage performance of GaN HEMT, reduce the gate size, improve the withstand voltage performance, The effect of easy process conditions

Active Publication Date: 2020-10-16
浙江集迈科微电子有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a step-type GaN gate device and its preparation method, which are used to solve the problem that the withstand voltage performance of GaN HEMT cannot be effectively improved in the prior art

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  • Step-type gan gate device and preparation method thereof
  • Step-type gan gate device and preparation method thereof
  • Step-type gan gate device and preparation method thereof

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Embodiment 1

[0051] see Figure 1 to Figure 10 , this embodiment provides a method for preparing a stepped GaN gate device, which is characterized in that it includes the following steps:

[0052] 1) Provide a substrate, epitaxially grow a GaN channel layer and a barrier layer on the substrate, and define a gate region, a source region and a drain region;

[0053]2) removing the barrier layer of the source region and the drain region, and epitaxially growing a doped GaN layer on the source region and the drain region, the upper surface of the doped GaN layer being higher than the the upper surface of the barrier layer;

[0054] 3) Depositing an isolation layer on the gate region, the source region, and the drain region, and defining the isolation layer distributed in the vertical direction as a sidewall layer;

[0055] 4) Divide the area of ​​the gate region except the sidewall layer into a zeroth etching region and a zeroth step region, the zeroth etching region, the zeroth step region ...

Embodiment 2

[0087] like Figure 10 As shown, this embodiment provides a stepped GaN gate device, which is characterized in that it includes:

[0088] A substrate 100, on which a gate region 100a, a source region 100b and a drain region 100c are defined

[0089] A channel layer 101 and a barrier layer 102 are sequentially formed on the substrate 100, and the barrier layer 102 is located in the gate region 100a;

[0090] a doped GaN layer 104 formed in the source region 100b and the drain region 100c, the upper surface of which is higher than the upper surface of the barrier layer 102;

[0091] The sidewall isolation layer 105b formed on the sidewall of the doped GaN layer 104 and the step isolation layer 105c formed above the barrier layer 102; the region of the gate region 100a except the sidewall isolation layer 105b Divided into an etching region and a step region, the step region is adjacent to the doped GaN layer 104 on one side of the gate region 100a; the step isolation layer 105c...

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Abstract

The invention provides a stepped GaN gate device and its preparation method. The preparation method comprises the following steps: providing a substrate, growing a GaN channel layer and a barrier layer, defining gate, source, and drain regions; removing the source-drain region barrier layer, and grow a doped GaN layer in the source and drain regions, and the upper surface of the doped GaN layer is higher than the barrier layer; deposit an isolation layer, and define the isolation layer in the vertical direction as a side wall layer; except the side wall layer in the gate area The area is divided into a zero etching area and a zero step area, and the zero etching area, the step area and the gate area have the same extension direction; the isolation layer of the zero etching area is removed; and a gate metal layer is deposited in the gate area. The present invention forms the step-type field plate of the grid through the isolation sidewall process, and at the same time reduces the size of the grid, and also improves the withstand voltage performance of the device by using the step-type field plate. The size of the grid in the invention is controllable, and the precision of the photolithography equipment is not high; the stepped field plate structure and the grid structure are formed together, and the process conditions are simple and feasible, and the repeatability is high.

Description

technical field [0001] The invention relates to the field of semiconductor integrated circuit manufacturing, in particular to a stepped GaN gate device and a preparation method. Background technique [0002] GaN high electron mobility transistors (HEMTs) have good application prospects in high-voltage scenarios due to their large energy band gaps. [0003] At present, in order to further improve the withstand voltage performance of GaN HEMT devices, generally by increasing the distance L from the gate to the drain gd , or add a field plate structure above the gate toward the drain to adjust the electric field distribution at the drain end and enhance the withstand voltage of the device. [0004] However, increasing the gate-to-drain distance L gd The process method not only increases the device area, which is not conducive to the miniaturization of the device, but also increases the access resistance and weakens the frequency performance of the device; while the process me...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/335H01L29/778H01L29/423H01L29/40H01L29/207
CPCH01L29/207H01L29/402H01L29/42312H01L29/66462H01L29/778
Inventor 冯光建蔡永清陈桥波黄雷
Owner 浙江集迈科微电子有限公司
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