37results about How to "Reduce gate size" patented technology

An advanced transistor with punch through suppression includes a gate with length Lg, a well doped to have a first concentration of a dopant, and a screening region positioned under the gate and having a second concentration of dopant. The second concentration of dopant may be greater than 5×1018 dopant atoms per cm3. At least one punch through suppression region is disposed under the gate between the screening region and the well. The punch through suppression region has a third concentration of a dopant intermediate between the first concentration and the second concentration of dopant. A bias voltage may be applied to the well region to adjust a threshold voltage of the transistor.

In a sense amplifier circuit having a plurality of sense amplifier portions arranged in order, each of the sense amplifier portions includes a transistor that supplies a bit line potential to a bit line pair in a corresponding column of a memory cell array and a gate electrode for supplying a precharge signal to a gate of the transistor. The gate electrode of the plurality of sense amplifier portions is provided as one piece as a whole and extends in a direction parallel to a row direction in the memory cell array. A gate electrode portion which is a connected portion between the gate electrode in a k-th sense amplifier portion and the gate electrode in a (k+1)-th sense amplifier portion is ring-shaped, where k is an odd number.

A semiconductor memory device has a memory region which is formed on a semiconductor substrate and in which a plurality of memory cells each including a memory transistor are arranged as a matrix using a plurality of impurity diffusion layers (bit lines) and a plurality of gate electrodes (word lines) intersecting each other. The gate electrode of each of the memory transistors has an upper surface thereof formed into a protruding portion which is higher in level at the middle portion than at the edge portions. A silicide layer is formed on the upper surface of the protruding portion of the gate electrode of each of the memory transistors.

A cipher processing apparatus wherein the gate scale of hardware has been reduced as compared with a conventional one using a substitution cipher table and wherein a high misleading characteristic has been achieved. A data converting part included in an encrypting apparatus divides an input data of 256 bits into block data A1, B1, A2 and B2 of 32 bits each. A first fusing part (43) provides an exclusive-OR of A1 and B1 and also provides an exclusive-OR of A2 and B2. A first misleading part (44) branches each of A1, A2 and the results of exclusive-OR (C1,C2) into three block data, and cyclically shifts two of those three block data and then fuses all of the block data. A second fusing part (45) provides an exclusive-OR of D1 and E2, which are results from the first misleading part (44), and also provides an exclusive-OR of E1 and D2 that are also results from the first misleading part (44). A block coupling part (46) couples the calculation results of the second fusing part (45). A second misleading part (47) branches each of the coupled data into three block data, and cyclically shifts two of those three block data and then fuses all of the block data.

The present invention belongs to the technical field of micro-electronic components, and especially provides a method for manufacturing a 10-nanometer T-shaped gate through electron beam lithography. The method adopts the technology combining electron beam overlap lithography with reactive ion etching, and comprises the steps of applying electron beam photoresist to the surface of an epitaxial layer of a device substrate in a spin coating way, designing a layout through electron beam lithography, performing metal evaporation, stripping the evaporated metal, then performing reactive ion etching to form a table top, applying the electron beam photoresist to a sample with the etched table top in a spin coating way, utilizing the precise electron beam overlap lithography to form a T-shaped morphology, performing metal evaporation again, and stripping the evaporated metal to form a T-shaped metal electrode, thereby manufacturing a 10-nanometer T-shaped gate between a source electrode and a drain electrode of the device through the electron beam lithography. The method of the present invention not only can greatly reduce the foot size of the T-shaped gate, but also can manufacture the T-shaped gate having a very wide head, thereby reducing gate resistance of the device and raising cut-off frequency of the device, therefore, the method has important significance in a process for manufacturing GaN-based and InP-based high-electron-mobility transistors.

A gate driver and a method for adjusting output channels thereof are provided. The method includes: setting a target number of the output channels; dividing the output channels into a first channel chain and a second channel chain; enabling a scanning operation of the first channel chain according to a clock signal and counting the clock signal to obtain a counting value; and when the counting value reaching a threshold value, enabling a scanning operation of the second channel chain, wherein the threshold value is determined according to a difference value between the target number and the physical number.

The invention provides a stepped GaN gate device and its preparation method. The preparation method comprises the following steps: providing a substrate, growing a GaN channel layer and a barrier layer, defining gate, source, and drain regions; removing the source-drain region barrier layer, and grow a doped GaN layer in the source and drain regions, and the upper surface of the doped GaN layer is higher than the barrier layer; deposit an isolation layer, and define the isolation layer in the vertical direction as a side wall layer; except the side wall layer in the gate area The area is divided into a zero etching area and a zero step area, and the zero etching area, the step area and the gate area have the same extension direction; the isolation layer of the zero etching area is removed; and a gate metal layer is deposited in the gate area. The present invention forms the step-type field plate of the grid through the isolation sidewall process, and at the same time reduces the size of the grid, and also improves the withstand voltage performance of the device by using the step-type field plate. The size of the grid in the invention is controllable, and the precision of the photolithography equipment is not high; the stepped field plate structure and the grid structure are formed together, and the process conditions are simple and feasible, and the repeatability is high.

Disclosed is a decoder, receiving the first and the second reference voltage groups and selecting a reference voltage in accordance with a received digital signal, including a first sub-decoder receiving the first reference voltage group, a second sub-decoder receiving the second reference voltage group 20B, and a third sub-decoder receiving a reference voltage selected by the second sub-decoder and outputting the selected reference voltage to the first sub-decoder or an output terminal of the decoder. The first sub-decoder includes a transistor of a first conductivity type having a back gate supplied with a first power supply voltage, the second sub-decoder includes a transistor of the first conductivity type having a back gate supplied with a second power supply voltage, and the third sub-decoder includes a transistor of the first conductivity type having a back gate supplied with a first power supply voltage.

Provided is an image display device including thin film transistors on a substrate, including: gate lines and drain lines intersecting the gate lines, each thin film transistor having, in a channel region, a laminate structure in which a gate electrode, a gate insulating film, and a semiconductor layer are laminated in the stated order from the substrate side; and a pair of removal regions in which parts of the gate insulating film are removed, which are formed on both sides of the gate electrode and formed in a channel width direction of the channel region, in which when W represents a width of the gate electrode in the channel width direction of the channel region, and R represents a width of the gate insulating film in the channel width direction, which is sandwiched between the pair of removal regions, R≧W is satisfied.