Junctionless semiconductor channel gate array storage structure and preparation method thereof

Abstract

The present invention provides a junctionless semiconductor channel gate array storage structure and a preparation method thereof. The structure comprises: a semiconductor substrate; an insulation layer located on the semiconductor substrate; a carbon nano tube gate array located on the insulation layer; a gate charge trapping structure located on the carbon nano tube gate array; a semiconductor channel, employing two-dimensional semiconductor materials, located on the gate charge trapping structure; and a source contact electrode and a drain contact electrode respectively located at two endsof the carbon nano tube gate array and connected with the semiconductor channel. The storage structure employs two-dimensional semiconductor material channel to replace a traditional silicon-doping channel and employs the metal carbon nano tube gate array to improve the gate charge tripping performance, simplify the device structure and further improve the storage array density.

Description

technical field [0001] The invention relates to the technical field of integrated circuits, in particular to a junctionless semiconductor trench gate array memory structure and a preparation method thereof. Background technique [0002] For NAND memories with different architectures, they can be divided into three-dimensional floating gate memories and three-dimensional charge trap memories according to the material of the storage layer. For the former three-dimensional floating gate memory, because the polysilicon floating gate is used as the storage layer, the area of ​​the storage unit is larger, and it is more difficult to realize the stacking of more layers of storage units. Therefore, the area is mainly realized by placing the peripheral circuit under the storage array. reduction. For the latter three-dimensional charge trap memory, it can be divided into vertical gate type and vertical channel type. The three-dimensional charge-trapping flash memory structure based ...

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Problems solved by technology

[0005] However, in the existing vertical channel type three-dimensional charge trapping memory, the device channel material adopts polysilicon film, which requires good crystallinity and large crystal grains, and at the same time requires the thickness of the polysilicon film channel to be as thin as possible. Difficult to balance, affecting product yield

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