Multi-channel parallel isolation analog/digital (A/D) acquisition and processing method
A collection and processing, multi-channel technology, applied in the field of sensor measurement, can solve the problems of poor real-time performance, inability to achieve multi-channel simultaneous sampling, and inability to adjust, etc., to achieve strong real-time performance, multi-channel synchronous acquisition, and high reliability.
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Embodiment 1
[0016] Example 1. refer to Figure 1-2 . A multi-channel parallel isolation A / D acquisition and processing method, the circuit of the method is composed of an input isolation circuit, a signal conditioning circuit, a digital isolator and an FPGA, and performs parallel input isolation acquisition for analog voltage signals output by multi-channel and different types of sensors , the analog voltage signal input by each channel is transmitted to the FPGA through the input isolation circuit, signal conditioning circuit and digital isolator in turn; the ground potential of the end connected to the input isolation circuit of each channel and the signal conditioning circuit is different, and there is no connection between the channels The interconnection of the ground loop; the signal conditioning circuit is composed of a gain adjustment circuit and a high-precision Σ-ΔA / D converter. The analog voltage signal is sent to the gain adjustment circuit after being input to the isolation ...
Embodiment 2
[0017] Example 2. refer to image 3 . In the acquisition processing method described in embodiment 1, the internal circuit of the FPGA includes an input unit, an output unit, a clock frequency divider, a driver, a synchronous signal control logic, a shift register, a latch and a memory; an external input The clock CLOCK enters the clock divider through the input unit, and then transmits the main clock MCLK signal to the output unit through the driver, and at the same time, the external input clock CLOCK is transmitted to the output unit through the synchronous signal control logic to generate the control signal CONV; the serial number of each channel The quantity SDO, the serial shift clock SCLK and the conversion completion flag signal READY are transmitted to the output unit sequentially through the shift register, latch and memory; the input unit and the output unit complete the interface processing function; the clock divider and the driver are used to generate The main ...
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