Square planar guide-pin-free semiconductor packaging part and manufacturing method thereof

Abstract

The invention relates to a quadrangular planar pinless semiconductor package and a manufacturing method thereof. A quadrilateral flat semiconductor package without pins, comprising: a chip holder; a plurality of electrical connection pads arranged around the chip holder, and the bottom surface of the chip holder and each of the electrical connection pads is covered with a copper layer; the chip , connected to the top surface of the chip holder; a plurality of bonding wires, respectively electrically connecting the chip and the electrical connection pad; encapsulating gel, covering the chip, the bonding wire, the chip holder and the electrical connection pad , but exposing the copper layer on the bottom surface of the chip base and the electrical connection pad; and a dielectric layer formed on the bottom surface of the encapsulant, and the dielectric layer is formed with a plurality of corresponding parts exposing the copper layer The opening, wherein the copper layer and the dielectric layer have a better joint degree can prevent solder from penetrating into the chip seat and solder protrusion defects at the interface between the electrical connection pad and the dielectric layer during reflow, thereby improving the product yield. Also provided is a method for manufacturing a quadrilateral plane semiconductor package without leads.

Description

technical field [0001] The invention relates to a quadrangular planar pinless semiconductor package and a manufacturing method thereof, in particular to a quadrangular planar pinless semiconductor package capable of preventing solder extrusion and a manufacturing method thereof. Background technique [0002] The quadrilateral planar pinless semiconductor package is a package unit in which the chip base and the bottom surface of the pins are exposed on the bottom surface of the encapsulant. Generally, the surface coupling technology is used to couple the package unit to the printed circuit board, thus forming a specific package. functional circuit modules. In the surface-coupled process, the die paddle and leads of the quad planar leadless semiconductor package are soldered directly to the printed circuit board. [0003] For example, U.S. Patent Nos. 6,238,952, 6,261,864 and 6,306,685 disclose a conventional quadrilateral planar leadless semiconductor package, the following ...

AI Technical Summary

Problems solved by technology

However, because the wetting ability of the solder ball 87 on the gold layer or the palladium layer is better, but the bonding degree between the dielectric layer 86 and the gold layer or the palladium layer is poor, the solder easily penetrates into the pin 813 and the dielectric layer 86 interface, resulting in the defect of solder extrusion (solder extrusion) 862, which prevents the formation of solder balls, and even causes electrical short circuits between adjacent solder balls

It not only affects the subsequent surface mount (SMT) manufacturing process, but also increases the cost and reduces the product yield

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