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Parallel advanced technology attachment (PATA) hard disk controller

A technology of hard disk controller and timing generator, applied in the direction of input/output to record carrier, etc., can solve the problems of difficult to use clock, large deviation of DSTROBE clock signal, poor stability control of high-frequency clock generator, etc., to achieve flexible Matching, low-cost compatible effects

Active Publication Date: 2015-02-11
MEMORIGHT (WUHAN) CO LTD
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  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Due to resource constraints and the need for cost control, it is difficult to use such a high-frequency clock; on the other hand, due to process constraints, the stability of the high-frequency clock generator is poorly controlled, resulting in a greater deviation of the DSTROBE clock signal generated after counting and accumulation

Method used

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  • Parallel advanced technology attachment (PATA) hard disk controller
  • Parallel advanced technology attachment (PATA) hard disk controller
  • Parallel advanced technology attachment (PATA) hard disk controller

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Embodiment Construction

[0018] Such as figure 1 Shown is the timing diagram of DMA command data transmission in the ATA protocol. The ATA commands accepted by the ATA device include PIO commands and DMA commands. Among them, the PIO command can be carried out under the clock frequency of 100M and 133M. While the DMA command needs to follow the figure 1 The timing shown is performed. The data is transmitted twice in one clock cycle, and there is one data transmission during the rising and falling periods of the clock. In different UDMA modes, the cycle of the clock signal and the setup and hold time of the data are different, as follows figure 1 shown.

[0019] When a clock signal needs to be generated, the minimum clock period of the 100M reference clock is 10ns, and the generated clock can support UDMA modes including UDMA5 / 4 / 2 / 1 / 0; the minimum clock period that can be generated by the 133M reference clock is 7.5ns, which can The generated clock can support UDMA modes including UDMA6 / 4 / 3 / 2 / 0. ...

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Abstract

The invention relates to a parallel advanced technology attachment (PATA) hard disk controller. The PATA hard disk controller comprises a time sequence generator and a data register, and is characterized by comprising a command analyzing unit, an ultra direct memory access (UDMA) mode selecting unit, a dual clock generator and a clock switching unit. A 133M and 100M dual clock generator is arranged in the PATA dick controller for flexibly matching the PATA disk with the UDMA transmission modes UDMA0--UDMA6 and selectively switching the dual clock according to the speed mode of a UDMA interface of a mainboard, so that low-cost compatibility between the PATA disk and the mainboard with different UDMA transmission modes is realized.

Description

technical field [0001] The invention relates to a PATA hard disk controller. Background technique [0002] The PATA hard disk needs to generate corresponding timing control signals and data signals according to the ATA protocol. ATA-6 can make the external transfer rate of the hard disk reach 100MB / s, and it is fully backward compatible. ATA-7 is the last version of the ATA interface, supporting 133MB / s data transfer speed. In the ATA protocol, the Ultra DMA (UDMA) transmission mode is mostly used, and the UDMA transmission mode has different transmission rates from UDMA0 to UDMA6 from the lowest 16.7M to 133M, as shown in Table 1. [0003] Table 1 UDMA data transmission timing [0004] [0005] As a parallel control device, the PATA hard disk is equipped with a clock generator in its hard disk controller to control the clock signal and the corresponding data signal. Among them, the minimum clock period of the 100M reference clock is 10ns, and the generated clocks tha...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F3/06
Inventor 陈毅成秦义杨清
Owner MEMORIGHT (WUHAN) CO LTD
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