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Low power consumption integrated circuit testing device with compressible data and method using same

A technology for integrated circuits and testing devices, applied in the field of low-power integrated circuit testing devices, can solve problems such as weakening the compression effect of test data, and achieve the effect of reducing jumps and realizing compression.

Active Publication Date: 2012-01-04
TSINGHUA UNIV
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

Although this method can reduce power consumption very well, the effect of test data compression will be weakened

Method used

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  • Low power consumption integrated circuit testing device with compressible data and method using same
  • Low power consumption integrated circuit testing device with compressible data and method using same
  • Low power consumption integrated circuit testing device with compressible data and method using same

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Embodiment Construction

[0050] The specific implementation manners of the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. The following examples are used to illustrate the present invention, but are not intended to limit the scope of the present invention.

[0051] Such as figure 1 As shown, the data-compressible low-power integrated circuit testing device of the present invention includes: scan forest, XOR gate network, output selection circuit, first control register and second control register; wherein,

[0052] The scan forest includes multiple scan input terminals and multiple scan flip-flop groups connected to each other, the scan input terminals are connected to all scan flip-flops in the first scan flip-flop group, and all scan flip-flops in each scan flip-flop group The scan flip-flops are connected to the output terminals of the scan flip-flops in the previous scan flip-flop group, the multiple scan input terminals ...

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PUM

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Abstract

The invention discloses a low power consumption integrated circuit testing device with compressible data and a method using the same. The device comprises a scanning forest, an XOR gate network, an output selection circuit, a first control register and a second control register, wherein the scanning forest comprises a plurality of scanning input ends and a plurality of mutually connected scanning trigger groups; the scanning input ends are connected to all scanning triggers in the first scanning trigger group; all scanning triggers in each scanning trigger group are connected with the output ends of the scanning triggers in the previous scanning trigger group; the input end of each XOR gate in the XOR gate network is connected with the output ends of the scanning triggers in the last group of scanning trigger group; and the output selection circuit is connected with the XOR gate network. According to the low power consumption integrated circuit testing device, node hop in the circuit can be reduced, energy consumption is lowered, and meanwhile compression of test response data can be achieved.

Description

technical field [0001] The invention relates to the technical field of digital integrated circuit testing, in particular to a data-compressible low-power integrated circuit testing device and a method thereof. Background technique [0002] In the field of digital circuit testing, many low-power testing methods and data compression methods have been proposed, but most of the low-power testing methods cannot be used to compress test data, and most of the data compression methods cannot be used to reduce power consumption. [0003] The methods that can reduce power consumption and compress data at the same time mainly include: [0004] (1) Assign a value to the unknown bit (X bit) of the test vector to reduce power consumption and compress data at the same time. Such a method can only find a compromise between data compression and power consumption reduction. If the power consumption is greatly reduced, the data compression effect will not be obvious; on the contrary, if the d...

Claims

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Application Information

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IPC IPC(8): G01R31/319
CPCG01R31/318547G01R31/319
Inventor 向东陈振
Owner TSINGHUA UNIV
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