Method and system for detecting false capacity memory

A memory and false capacity technology, applied in the detection field, can solve the problems of imperfect detection methods and slow detection speed of false capacity memory

Active Publication Date: 2012-01-04
SHENZHEN NETCOM ELECTRONICS CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] The purpose of the embodiments of the present invention is to provide a detection method for a false capacity memory, aiming to solve the problems in the prior art that the detection method of the false capacity memory is not perfect and the detection speed is slow with the continuous improvement and improvement of the false capacity technology

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  • Method and system for detecting false capacity memory
  • Method and system for detecting false capacity memory

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Experimental program
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Embodiment 1

[0039] figure 1 It shows the implementation flow of the detection method of the false capacity memory provided by the embodiment of the present invention, and its specific steps are as follows:

[0040] In step S101, the preset test data is written in the high address data area of ​​the memory.

[0041] In the embodiment of the present invention, it is necessary to pre-configure and generate test data before performing this step. The specific implementation steps are given below, and will not be repeated here, but they are not intended to limit the present invention.

[0042]Wherein, the memory may be a Nand Flash flash memory, and the following uses the Nand Flash flash memory as an example for description.

[0043] In step S102, the data corresponding to the high address data area of ​​the memory is read out, and when the data corresponding to the high address data area of ​​the memory read out is different from the written test data, it is determined that the memory is Th...

Embodiment 2

[0050] figure 2 It shows the implementation process of generating test data with preset settings provided by the embodiment of the present invention, and its specific steps are as follows:

[0051] In step S201, a test identifier is randomly generated, and the test data includes the test identifier for detecting the false capacity of the memory.

[0052] In the embodiment of the present invention, the test mark is stored in a buffer with a length of 512 bytes. As a specific embodiment of the present invention, the test mark can adopt 2 DWORD (double word), when 2 DWORD , its random repetition probability is set to 1 / 18446744073709551616 of 2 to the 64th power.

[0053] In step S202, the test identifier is added to the sector template.

[0054] In step S203, the sector template is copied to the test data area with a length of 64K to obtain test data written into several sectors in the tail area and the middle area of ​​the memory.

[0055] In the embodiment of the present i...

Embodiment 3

[0057] Figure 4 It shows the implementation flow of starting from the 0 address sector of the memory, comparing the read sector data with the test identification, and judging whether the memory is a cyclic write type pseudo-capacity memory provided by the embodiment of the present invention. The steps are as follows:

[0058] In step S401, the sector data at address 0 of the memory is read.

[0059] In the embodiment of the present invention, sector data is read starting from the logical address 0 sector.

[0060] In step S402, it is judged whether the data at the specified position of the sector data contains the test identifier contained in the test data, if yes, execute step S403, otherwise execute step S404.

[0061] In the embodiment of the present invention, at the identification bit (the data that must be carried in the sector data) at the specified position of the read sector data, it is judged whether the identification bit is the same as the test identification co...

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Abstract

The invention is applied to the technical field of detection, and provides a method and a system for detecting a false capacity memory. The method comprises the following steps of: writing preset test data in a high address data area of a memory; reading data corresponding to the high address data area of the memory; determining that the memory is the false capacity memory of a false writing type when the read data corresponding to the high address data area of the memory is different from the written test data, and completing a detection flow; and writing the preset test data in a plurality of sectors of a tail region and a middle region of the memory when the read data corresponding to the high address area of the memory is the same as the written test data; and comparing test identifiers of read sector data from an address 0 sector of the memory, and judging whether the memory is the false capacity memory of a circulated writing type. The invention is high in detection speed and convenient.

Description

technical field [0001] The invention belongs to the technical field of detection, and in particular relates to a detection method and system of a false-capacity memory. Background technique [0002] With the wide application of Nand Flash in the field of memory, more and more electronic products and memories are using Nand Flash as storage media, such as U disk, memory card, SSD, etc. It has anti-vibration, low power consumption, long-term Efficient storage and other advantages. [0003] Nand Flash is a non-volatile memory that can be erased and reprogrammed in blocks of memory cells called blocks. The write operation of any Flash device can only be performed in empty or erased cells, so in most cases, the erase must be performed before the write operation. In the firmware program, in order to provide a continuous logical operation space, it is necessary to effectively manage the blocks of Flash, including the identification of bad blocks, the management of areas, and the ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C29/12
CPCG11C2029/5002G11C29/00
Inventor 覃敏邓恩华
Owner SHENZHEN NETCOM ELECTRONICS CO LTD
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