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Semiconductor package

一种半导体、封装件的技术，应用在半导体封装件领域，能够解决封装件电特性和可靠性劣化、上半导体芯片与基板连接不太可能合适等问题

Inactive Publication Date: 2012-08-22
SK HYNIX INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, since the edge of the upper semiconductor chip is suspended above the smaller lower semiconductor chip, there is space below it, so the connection of the upper semiconductor chip to the substrate is unlikely to be suitable
[0006] This can lead to degradation of the electrical characteristics and reliability of the package

Method used

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  • Semiconductor package
  • Semiconductor package
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Examples

Experimental program
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Embodiment Construction

[0021] Specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0022] It is to be understood that the drawings are not necessarily to scale and in some instances the scale may have been exaggerated in order to more clearly depict certain features of the invention.

[0023] figure 1 is a sectional view showing a semiconductor package according to an embodiment of the present invention.

[0024] refer to figure 1 , The semiconductor package according to an embodiment of the present invention includes: a body 100 having a trench H, a lower device A disposed in the trench H, and an upper device B disposed on the lower device A in the trench H of the body 100 .

[0025] The body 100 has an upper surface a and a lower surface b. Grooves H are defined on the upper surface a of the body 100 , and ball pads 101 are formed on the lower surface b of the body 100 .

[0026] For example, the body 100 may include a p...

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PUM

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Abstract

A semiconductor package includes a body having a first surface and a second surface facing away from the first surface, and formed with a groove in the first surface. First connection parts may electrically connect a portion of the first surface to a portion of the second surface of the body. Second connection parts may electrically connect a portion of a bottom portion of the groove to a portion of the second surface of the body. A lower device may be disposed in the groove of the body, and have third connection parts that are electrically connected with the second connection parts. An upper device may be disposed on the body and the lower device, and have fourth connection parts that are electrically connected with the first connection parts and the third connection parts.

Description

technical field [0001] The present invention relates to a semiconductor package, in particular to a semiconductor package capable of improving the electrical connection between a substrate and an upper semiconductor chip in a package-on-package structure. Background technique [0002] In order to meet demands for miniaturization and high capacity, packaging technologies for semiconductor devices have been developed. One such technology is stack package, which can meet the requirements of miniaturization, high capacity, and mounting efficiency. [0003] Examples of stack packages include COC (Chip On Chip) packages in which an upper semiconductor chip is stacked on a lower semiconductor chip. [0004] In the COC package, in order to electrically connect a lower semiconductor chip with an upper semiconductor chip, circuit wiring such as rearrangement wires or connection members such as bumps are formed. [0005] In some cases, a plurality of semiconductor chips having differ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L23/498H01L23/48H01L23/31
CPCH01L23/13H01L23/3128H01L25/0657H01L2225/06517H01L2225/06513H01L2225/06541H01L2225/06565H01L2224/131H01L2924/15153H01L2924/15311H01L2924/157H01L2924/18161H01L23/49827H01L2224/14181H01L2224/16145H01L2224/16225H01L2224/1403H01L2224/16146H01L2224/16235H01L2224/17181H01L2924/014
Inventor 梁胜宅
Owner SK HYNIX INC
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