General bus slave unit interface

A technology of general interface and unit interface, applied in instruments, electrical digital data processing, etc., can solve problems such as extending the SOC research and development cycle, and achieve the effect of shortening the research and development cycle, speeding up the integration speed, and reducing the workload

Active Publication Date: 2015-04-22
NO 771 INST OF NO 9 RES INST CHINA AEROSPACE SCI & TECH
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Problems solved by technology

This will greatly prolong the SOC R&D cycle and make IP multiplexing an empty talk

Method used

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Embodiment Construction

[0018] The present invention is described in further detail below in conjunction with accompanying drawing:

[0019] see Figure 1-2 , the technical scheme that the present invention adopts is: in order to make this universal bus slave unit interface really become universal interface, by analyzing the common problem of different commonly used interfaces, find that although the bus interface is different, the bus interface has some common functions, such as protocol conversion , data cache, etc. Using the hierarchical design method, the interface is divided into different functional modules, combined with practical application, it is integrated into a core, and a general slave unit interface module is developed. The main considerations in its universal design are as follows:

[0020] ●Bus adaptability considerations

[0021] For a peripheral core, it may need to be connected to different system buses. Therefore, as a general-purpose slave unit interface, it must support diff...

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Abstract

The invention discloses a general bus slave unit interface, which comprises a bus slave unit interface module, a clock processing unit, a synchronization unit, a RAM (random access memory) control logic generation unit, a data buffering unit FIFO (first input first out), a register unit and a special processing unit, wherein the RAM control logic generation unit, the register unit, the special processing unit and the clock processing unit are respectively in bidirectional connection with the bus slave unit interface module, and the synchronization unit is respectively in bidirectional connection with the special processing unit, the register unit, the RAM control logic generation unit and a slave unit. According to the invention, the general bus slave unit interface utilizes a bus reading-writing register unit or amends compiling parameters to select the operation mode and operation manner of the modules, so that different peripheral inner cores are connected with various buses, and the SOC (system on chip) development cycle is effectively shortened.

Description

Technical field: [0001] The invention belongs to the field of integrated circuits, and relates to a general bus slave unit interface HPPI (High Performance Peripheral Interface) in the SOC system integration process, in particular to a bus slave unit universal interface. Background technique: [0002] The integration level and product performance of integrated circuits double every 18 months, and the rapid improvement of integrated circuits in terms of scale, speed, and functions has put forward more stringent requirements for design methods. Due to the characteristics of low power consumption, small size, rich system functions, high performance and low cost, SoCs are becoming more and more widely used. In recent years, SoC has become a rapidly developing product category and design form and has shown the mainstream trend of integrated circuit design. [0003] The goal of SoC design is to reuse existing modules or "cores" to maximize reuse efficiency. Due to the increasing...

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F13/38G06F13/40
Inventor 盛廷义段青亚吴龙胜陈庆宇李小波
Owner NO 771 INST OF NO 9 RES INST CHINA AEROSPACE SCI & TECH
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