A mixed crystal plane double strained silicon-based cmos integrated device and its preparation method

An integrated device and mixed crystal plane technology, which is applied in the field of mixed crystal plane dual-strained silicon-based CMOS integrated devices and preparation, can solve the problem that the mobility cannot be optimized at the same time, and achieves improved electrical performance, improved mobility, and reduced power consumption. Effect

Inactive Publication Date: 2015-09-30
XIDIAN UNIV
View PDF4 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

At the same time, NMOS and PMOS are prepared on the same crystal plane, and their mobility cannot be optimized at the same time

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • A mixed crystal plane double strained silicon-based cmos integrated device and its preparation method
  • A mixed crystal plane double strained silicon-based cmos integrated device and its preparation method
  • A mixed crystal plane double strained silicon-based cmos integrated device and its preparation method

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0053] Embodiment 1: Prepare 22nm mixed crystal plane double-strained silicon-based CMOS integrated device and circuit, the specific steps are as follows:

[0054] Step 1, SOI substrate material preparation, such as figure 2 , image 3 shown.

[0055] (1a) Select the N-type doping concentration as 1×10 15 cm -3 The Si sheet 1 with a crystal plane of (110) is oxidized on the surface, and the thickness of the oxide layer is 0.5 μm, which is used as the upper substrate material, and hydrogen is injected into the substrate material;

[0056] (1b) Select the P-type doping concentration as 1×10 15 cm -3 The Si sheet 2 with a crystal plane of (100) is oxidized on its surface, and the thickness of the oxide layer is 0.5 μm, which is used as the base material of the lower layer;

[0057] (1c) Using a chemical mechanical polishing (CMP) process to polish the surface of the lower and upper substrate materials respectively;

[0058] (1d) SiO on the surface of the lower and upper s...

Embodiment 2

[0098] Embodiment 2: Prepare 30nm mixed crystal plane double-strained silicon-based CMOS integrated device and circuit, the specific steps are as follows:

[0099] Step 1, SOI substrate material preparation, such as figure 2 , image 3 shown.

[0100] (1a) Select the N-type doping concentration as 3×10 15 cm -3 The Si sheet 1 with a crystal plane of (110) is oxidized on the surface, and the thickness of the oxide layer is 0.75 μm, which is used as the upper substrate material, and hydrogen is injected into the substrate material;

[0101] (1b) Select the P-type doping concentration as 3×10 15 cm -3 The Si sheet 2 with a crystal plane of (100) is oxidized on its surface, and the thickness of the oxide layer is 0.75 μm, which is used as the base material of the lower layer;

[0102] (1c) Using a chemical mechanical polishing (CMP) process to polish the surface of the lower and upper substrate materials respectively;

[0103] (1d) SiO on the surface of the lower and upper...

Embodiment 3

[0143] Embodiment 3: Prepare 45nm mixed crystal plane double-strained silicon-based CMOS integrated device and circuit, the specific steps are as follows:

[0144] Step 1, SOI substrate material preparation, such as figure 2 , image 3 shown.

[0145] (1a) Select the N-type doping concentration as 5×10 15 cm -3 The Si sheet 1 with a crystal plane of (110) is oxidized on the surface, and the thickness of the oxide layer is 1 μm, which is used as the upper base material, and hydrogen is injected into the base material;

[0146] (1b) Select the P-type doping concentration as 5×10 15 cm -3 The Si sheet 2 with a crystal plane of (100) is oxidized on its surface, and the thickness of the oxide layer is 1 μm, which is used as the base material of the lower layer;

[0147] (1c) Using a chemical mechanical polishing (CMP) process to polish the surface of the lower and upper substrate materials respectively;

[0148] (1d) SiO on the surface of the lower and upper substrate mater...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

PropertyMeasurementUnit
thicknessaaaaaaaaaa
thicknessaaaaaaaaaa
thicknessaaaaaaaaaa
Login to View More

Abstract

The invention discloses a mixed crystal face double strain silicon substrate complementary metal oxide semiconductor (CMOS) integrated device and a preparation method. The preparation method comprises the following steps of: preparing a silicon on insulator (SOI) substrate provided with a (110) crystal face serving as an upper layer basis material and a (100) crystal face serving as a lower layer basis material; carving a deep groove in an N-channel metal oxide semiconductor (NMOS) area at the temperature of 600-800 DEG C, selectively growing a strain silicon epitaxial layer provided with the (100) crystal face and preparing a strain silicon channel NMOS on the epitaxial layer; selectively growing a strain SiGe epitaxial layer provided with the (110) crystal face in areas except for an NMOS active area and preparing a compressive strain SiGe channel P-channel metal oxide semiconductor (PMOS) of a channel on the epitaxial layer; and photoetching a lead to form a mixed crystal face CMOS integrated circuit with a 22-45nm conducting channel. The integrated device and the preparation method sufficiently use the characteristics that the electronic mobility of a tensile strain silicon material is higher than that of a body silicon material, the electronic mobility of a compressive strain siGe material is higher than that of the body silicon material and the migration rate is anisotropic, so that the mixed crystal face double strain silicon substrate CMOS integrated device with the improved performance and the circuit are prepared based on the SOI substrate.

Description

technical field [0001] The invention belongs to the technical field of semiconductor integrated circuits, and in particular relates to a mixed crystal plane double-strained silicon-based CMOS integrated device and a preparation method. Background technique [0002] In the contemporary era of highly developed information technology, microelectronic technology represented by integrated circuits is the key to information technology. As the fastest-growing, most influential and most widely used technology in human history, integrated circuits have become an important symbol to measure a country's scientific and technological level, comprehensive national strength and national defense strength. [0003] "Moore's Law", which has had a huge impact on the development of the microelectronics industry, states that the number of transistors on an integrated circuit chip doubles approximately every 18 months, and the performance also doubles. For more than 40 years, the world's microel...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & AuthorityPatents(China)
IPC IPC(8): H01L27/12H01L21/84
Inventor张鹤鸣李妤晨宋建军胡辉勇宣荣喜王斌王海栋郝跃
OwnerXIDIAN UNIV