usb full speed device data signal synchronization circuit
A technology of signal synchronization and device data, applied in the direction of electrical digital data processing, instruments, etc., can solve problems such as signal distortion, and achieve the effect of ensuring correctness
Active Publication Date: 2016-12-28
SHANGHAI HUAHONG INTEGRATED CIRCUIT
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At the same time, due to the inconsistent timing of the two data signal lines of the USB full-speed device, when synchronizing the USB bus data signal, the synchronized signal will be distorted, thus inserting some wrong pulse signals
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[0014] The two data signal lines of the USB full-speed device are used to transmit four bus data signals, such as figure 1 As shown, the value of D+ and D- is 10 for the J state, 01 for the K state, 00 for the SE0 state, and 11 for the SE1 state. Among them, the J state represents data 1, the K state represents data 0; and the SE0 state represents the end signal of a USB data packet, and the SE1 state is an invalid state and is not allowed to be used in USB data transmission.
[0015] When a USB full-speed device transmits a USB data packet, it always starts from the K state, and continuously sends the K state to indicate data 0 or J state to indicate the bit stream of data 1, until the end of the data signal, and sends the SE0 state to indicate the current USB data Package ends. Therefore, in the embodiment of the present invention, only the K state and the SE0 state indication signal are synchronized. After synchronization, if the state of the bus data signal is not in the ...
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The invention discloses a data signal synchronization circuit of a universal serial bus (USB) full-speed device and is characterized in that a high-frequency clock is used for synchronizing indicating signals in a K state and a search engine optimization (SEO) state; a two-stage D latch is adopted by a synchronization logic to eliminate the metastability problem of data signals; then, another D latch and a two-input AND gate are further used by the synchronization logic to eliminate error pulse signals which are sampled by the high-frequency clock falsely due to burrs on the indicating signals in the SEO state; and after the signals are synchronized, and the error pulses are eliminated, the indicating signals which are in the K state, the J state and the SEO state and are used by an internal logic for generating USB bus data signals are combined again. By adopting the data signal synchronization circuit of the USB full-speed device, the asynchronous data signals of the USB device suitable for a USB full-speed protocol can be synchronized, and the correctness of the signals after synchronization can be ensured.
Description
technical field [0001] The invention relates to the interface field of PC (personal computer), in particular to a USB full-speed device data signal synchronization circuit. Background technique [0002] The USB (Universal Serial Bus) interface was jointly proposed by Intel, Compaq, IBM, Microsoft and other companies at the end of 1994. It is an external bus standard used to regulate the connection and communication between computers and external devices. [0003] Since the initial version of USB was published in 1994, the USB interface has become the standard expansion interface in computers. The transmission speed of the USB interface is fast, 12Mbps (12 megabits per second) for full-speed devices, and 1.5Mbps for low-speed devices; it is easy to use and supports plug-and-play and hot-swapping of devices; in addition, it also has the advantages of flexible connection and independent power supply. The USB interface can be connected to almost all external devices such as mou...
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IPC IPC(8): G06F13/38
Inventor 叶国平
Owner SHANGHAI HUAHONG INTEGRATED CIRCUIT