Asynchronous signal synchronization circuit
A synchronous circuit and asynchronous signal technology, applied in the direction of logic circuit connection/interface layout, etc., can solve problems such as synchronization failure of multiple clock domains, and achieve the effect of eliminating metastability problems and simplifying the process.
Active Publication Date: 2018-04-27
SHANGHAI HUAHONG INTEGRATED CIRCUIT
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Problems solved by technology
In multi-clock domains, when designing circuits, the influence of timing on functions must be fully considered. A circuit that appears to have no problems on the surface may not actually achieve the designed function because of ignoring the importance of timing, resulting in Synchronization failure between multiple clock domains
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[0018] The asynchronous signal synchronous circuit is a synchronous circuit transmitted between different clock domains, which can not only complete the synchronous process of the asynchronous signal, but also prevent the metastability of the signal during the synchronous process.
[0019] see figure 1 As shown, the asynchronous signal synchronous circuit includes an input logic unit and an output logic unit.
[0020] The input logic unit includes a first D flip-flop D1, a first AND gate AND1 with two input terminals, an OR gate OR with two input terminals, and an invert gate INV.
[0021] The input terminal D of the first D flip-flop D1 is connected to the output terminal of the first AND gate AND1; the clock terminal CLK of the first D flip-flop D1 inputs the clock CLKA of the input clock domain; the first The output terminal Q of the D flip-flop D1 is connected to an input terminal of the OR gate OR, and the node connected thereto is denoted as D1Q; the other input termina...
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The invention discloses an asynchronous signal synchronous circuit, comprising: an input logic unit, which includes a first D flip-flop, a first AND gate, an OR gate, and a NOT gate; an output logic unit, which includes, A second D flip-flop, a third D flip-flop, and a second AND gate. The input logic unit is used to latch the input asynchronous pulse signal and the output signal of the first D flip-flop, and feed back the output signal of the first D flip-flop to the input terminal, so that the output of the first D flip-flop is always valid until it is read by the second The D flip-flop is sampled; and under the control of the feedback signal, the original latched input pulse signal is cleared to prepare for the next input pulse signal reception; the output logic unit is used to pass the latched input asynchronous pulse signal through the two-stage D flip-flop Tap to generate an output pulse signal with the clock width of the output clock domain to eliminate metastability. The invention can not only complete the synchronization of the asynchronous signal, but also prevent the metastable state of the signal during the synchronization process.
Description
technical field [0001] The invention relates to the field of digital circuits, in particular to an asynchronous signal synchronous circuit in which signals are transmitted between different clock domains. Background technique [0002] The processing of multiple clock domains is an important link in system-on-chip (SOC) design. Underestimating the specific problems that arise can have catastrophic consequences for the design. How to maintain the stability of the system and successfully complete the data transmission when data is transmitted across clock domains is a problem that every designer needs to pay attention to. [0003] Because of different clock domains, each flip-flop has its own set-up and hold time parameters. Within this time parameter, the input signal is not allowed to change near the rising edge of the clock. If a signal is sampled during its settling time, the result will be unpredictable, known as metastable. In multi-clock domains, when designing circui...
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IPC IPC(8): H03K19/0175
Inventor 丁兆健
Owner SHANGHAI HUAHONG INTEGRATED CIRCUIT