Synchronous circuit for asynchronous signals

Abstract

The invention discloses a synchronous circuit for asynchronous signals. The synchronous circuit comprises an input logic unit and an output logic unit, wherein the input logic unit comprises a first D trigger, a first AND gate, an OR gate and a NOT gate; the output logic unit comprises a second D trigger, a third D trigger and a second AND gate. The input logic unit is used for latching an input asynchronous pulse signal and an output signal of the first D trigger, feeding the output signal of the first D trigger back to an input end to enable the output of the first D trigger to be always effective until the output signal is sampled by the second D trigger, clearing the originally-latched input pulse signal under the control of a feedback signal and preparing for the next reception of the input pulse signal; the output logic unit is used for beating the latched input asynchronous signal through the two-stage D triggers to generate an output pulse signal capable of outputting a width of a clock of a clock domain so as to eliminate a semi-stable state. According to the synchronous circuit, synchronization of the asynchronous signals can be completed, and the semi-stable state of the signals in a synchronizing process can be prevented.

Description

technical field [0001] The invention relates to the field of digital circuits, in particular to an asynchronous signal synchronous circuit in which signals are transmitted between different clock domains. Background technique [0002] The processing of multiple clock domains is an important link in system-on-chip (SOC) design. Underestimating the specific problems that arise can have catastrophic consequences for the design. How to maintain the stability of the system and successfully complete the data transmission when data is transmitted across clock domains is a problem that every designer needs to pay attention to. [0003] Because of different clock domains, each flip-flop has its own set-up and hold time parameters. Within this time parameter, the input signal is not allowed to change near the rising edge of the clock. If a signal is sampled during its settling time, the result will be unpredictable, known as metastable. In multi-clock domains, when designing circui...

AI Technical Summary

Problems solved by technology

In multi-clock domains, when designing circuits, the influence of timing on functions must be fully considered. A circuit that appears to have no problems on the surface may not actually achieve the designed function because of ignoring the importance of timing, resulting in Synchronization failure between multiple clock domains

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