Method and circuit for eliminating errors and duty ratio detection circuit

An error elimination and circuit technology, applied in the field of circuits, can solve problems such as duty cycle error and measurement error

Active Publication Date: 2012-12-19
BCD (SHANGHAI) MICRO ELECTRONICS LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] In view of this, the present invention provides an error elimination circuit, method and duty cycle detection circuit, to overcome the duty cycle detection circuit in the prior art when measuring the duty

Method used

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  • Method and circuit for eliminating errors and duty ratio detection circuit
  • Method and circuit for eliminating errors and duty ratio detection circuit
  • Method and circuit for eliminating errors and duty ratio detection circuit

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0074] see Figure 7 , which is a schematic structural diagram of the first error elimination circuit provided by the embodiment of the present invention, the circuit includes:

[0075] Compensation phase shifting module 701 and counting control module 702;

[0076] The quantization signal acts on an input end of the compensation phase shifting module 701, the sampling signal acts on the other input end of the compensation phase shifting module 701, and the output end of the compensation phase shifting module 701 is connected to the input end of the counting control module 702;

[0077] The compensation phase shifting module 701 sequentially shifts the phases of each quantized high level in the current set of quantized high levels, so that the rising edge of each phase-shifted quantized high level is synchronized with the rising edge of the sampling signal, and each phase shifted The length of the final quantized high level is an integer multiple of the sampling signal period...

Embodiment 2

[0088] When i is equal to 1, the error elimination circuit is as follows.

[0089] see Figure 8, is a schematic structural diagram of a second error elimination circuit provided by an embodiment of the present invention, the circuit includes: a capacitor C, a charging and discharging module 801, a judging module 802, and a counting control module 702, wherein:

[0090] One end of the capacitor C is grounded, and the other end is connected to the output terminal of the charging and discharging module 801 and the input terminal of the judgment module 802 respectively; The output terminal of 802 is connected to the input terminal of the counting control module 702; the sampling signal clk acts on the control terminal of the judging module 802 and the control terminal of the counting control module 803 respectively.

[0091] It works as follows:

[0092] When the first rising edge of the quantized signal Ton arrives (when the rising edge of the quantized high level 1 arrives), ...

Embodiment 3

[0126] When i is greater than 1, the error elimination circuit is as follows.

[0127] The embodiment of the present invention also provides a third error elimination circuit, which includes:

[0128] Capacitor C, charging and discharging module 1301, judging module 1302 and counting control module 702, wherein:

[0129] One end of the capacitor C is grounded, and the other end is connected to the output terminal of the charging and discharging module 1301 and the input terminal of the judgment module 1302; The output terminal of 1302 is connected to the input terminal of the counting control module 702; the sampling signal clk acts on the control terminal of the judgment module 1302 and the control terminal of the counting control module 702 respectively.

[0130] The rising edge of the quantized high level after the compensation phase shift is the moment when the capacitor C stops charging, and the falling edge of the quantized high level after the compensation phase shift ...

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PUM

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Abstract

An embodiment of the invention discloses a method and a circuit for eliminating errors and a duty ratio detection circuit. The circuit for eliminating errors comprises a compensation phase-shift module and a counting control module. Quantized signals are acted on an input end of the compensation phase-shift module, sampling signals are acted on another input end of the compensation phase-shift module, and an output end of the compensation phase-shift module is connected with an input end of the counting control module. By the aid of the circuit for eliminating error, an error of the average duty ratio obtained only exists on a quantized high level or the last sampling signal, and errors are greatly reduced.

Description

technical field [0001] The invention relates to the field of circuits, and more specifically relates to an error elimination circuit, method and duty ratio detection circuit. Background technique [0002] see figure 1 , is a schematic diagram of a duty ratio detection circuit in the prior art, wherein clk represents a sampling signal, and Ton represents a quantized signal. The duty ratio detection circuit includes: a counting module 102 and a first AND gate circuit 101, the quantization signal and the sampling signal act on different input terminals of the first AND gate circuit 102 respectively, the principle of the duty ratio detection circuit is as follows: in a preset In the time period T, when the quantization signal is at a high level and the sampling signal is at a rising edge, the counting module 101 counts the number of sampling signals until the quantization signal reaches a falling edge and stops counting, and the length of the high level of the quantization sign...

Claims

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Application Information

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IPC IPC(8): H03K5/19
Inventor 罗东旭宗强方绍华
Owner BCD (SHANGHAI) MICRO ELECTRONICS LTD
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