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A verification method and system for a SOC chip

A verification method and chip technology, applied in CAD circuit design, special data processing applications, instruments, etc., can solve problems such as complex verification operations, inability to verify application scenarios, inability to simulate system software and hardware co-verification, etc., to achieve easy-to-use and easy-to-use The effect of multiplexing

Active Publication Date: 2015-12-09
ACTIONS ZHUHAI TECH CO
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0008] The purpose of the embodiments of the present invention is to provide a verification method for SOC chips, which aims to solve the problem of complex verification operations in the prior art for existing verification platforms, and the inability to verify complex application scenarios and the inability to realize software and hardware collaborative verification on the simulation system The problem

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  • A verification method and system for a SOC chip
  • A verification method and system for a SOC chip
  • A verification method and system for a SOC chip

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0038] figure 2 It shows the implementation flowchart of the SOC chip verification method provided by Embodiment 1 of the present invention, and is described in detail as follows:

[0039] In step S201, a test program is loaded.

[0040] In the embodiment of the present invention, the test program can realize the following functions:

[0041] (1) Control the flow of the verification system.

[0042] (2) Obtain and change the state of the authentication system.

[0043] (3) Operate and access the chip to be tested.

[0044] (4) Generate random test transactions to test the chip.

[0045] (5) Operations that other standard C / C++ can complete.

[0046] In the embodiment of the present invention, the test program may be a driver program or an application program, for example, may include a main program and an interrupt service program, etc., wherein,

[0047] 1. The interrupt service routine can be a function with the following form:

[0048] intisr(intpid, intsource, intp...

Embodiment 2

[0133] Figure 4 It shows the flow chart of the method for generating a random transaction according to the system function and the maintenance list corresponding to the system function when the random transaction is a random test transaction provided by the second embodiment of the present invention, and is described in detail as follows:

[0134] In step S401, the device under test configuration corresponding to the aforementioned device under test is searched in the device under test configuration list.

[0135] In the embodiment of the present invention, each device under test has a device under test configuration, the device under test configuration includes the register image of the device under test and the constraint expression of the device under test, and the above register image specifically includes the name and address of the register , bit width, default configuration value, current configuration value and previous configuration value, the above constraint expres...

Embodiment 3

[0146] Figure 6 It shows the implementation flowchart of the method for generating a random transaction according to the system function and the maintenance list corresponding to the system function when the random transaction is a random IO operation transaction provided by the third implementation of the present invention, and is described in detail as follows:

[0147] In step S601, the random parameters to be randomized in the random IO function are determined.

[0148] In step S602, the random values ​​of the above random parameters are generated in chronological order through the IO list.

[0149] In step S603, a random IO operation transaction is generated according to the random value of the above random parameter.

[0150] For ease of understanding, the method of the embodiment of the present invention is described below with a specific implementation example, but not limited to this implementation example. For details, please refer to Figure 7 , when the random t...

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Abstract

The present invention is applicable in the technical field of chip. Provided in embodiments of the present invention is a method for verifying an SOC chip. The method comprises the following steps: loading a testing procedure; scheduling a corresponding system function from a system interface function library on the basis of the testing procedure, and generating a random event on the basis of the system function and of a maintenance list corresponding to the system function; and verifying the test-awaiting SOC chip on the basis of the random event. The present invention allows the testing procedure compiled by a software engineer to run directly on an existing verification platform, thereby implementing co-verification of software and hardware, while at the same time packages low-level information, thus allowing for convenient use and reuse of verification system.

Description

technical field [0001] The invention belongs to the technical field of chips, and in particular relates to a verification method and system of an SOC chip. Background technique [0002] After the chip design is completed, it needs to be verified. The main task of verification is to verify the correctness of the design and determine whether the chip meets all design specifications. [0003] The traditional verification method is direct vector test (direct vector test). Direct vector test is a signal level verification. It communicates directly with the chip to be verified at the signal level by manufacturing a fixed scene stimulus, and checks the value and change of the chip pin signal. To verify the function of the chip. This verification method requires that the working scene of the chip must be designed in advance, and the verification personnel directly deal with very low-level signal-level information. With this verification method, the workload of the verification per...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F17/50
CPCG06F17/5022G06F30/33
Inventor 李新辉
Owner ACTIONS ZHUHAI TECH CO